mirror of https://github.com/YosysHQ/yosys.git
Fixed segfault on invalid verilog constant 1'b_
This commit is contained in:
parent
405cf67b64
commit
4b8200eb49
|
@ -122,7 +122,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
|
||||||
}
|
}
|
||||||
|
|
||||||
int len = GetSize(data);
|
int len = GetSize(data);
|
||||||
RTLIL::State msb = data.back();
|
RTLIL::State msb = data.empty() ? RTLIL::S0 : data.back();
|
||||||
|
|
||||||
if (len_in_bits < 0) {
|
if (len_in_bits < 0) {
|
||||||
if (len < 32)
|
if (len < 32)
|
||||||
|
|
Loading…
Reference in New Issue