mirror of https://github.com/YosysHQ/yosys.git
Added simple $dlatch support to opt_rmdff
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264eb8eb6e
commit
4b6221478e
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@ -29,6 +29,33 @@ PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map, dff_init_map;
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SigSet<RTLIL::Cell*> mux_drivers;
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bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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{
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SigSpec sig_e = dlatch->getPort("\\EN");
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if (sig_e == State::S0)
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{
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(dlatch->getPort("\\Q")))
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val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
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mod->connect(dlatch->getPort("\\Q"), val_init);
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goto delete_dlatch;
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}
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if (sig_e == State::S1)
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{
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mod->connect(dlatch->getPort("\\Q"), dlatch->getPort("\\D"));
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goto delete_dlatch;
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}
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return false;
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delete_dlatch:
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log("Removing %s (%s) from module %s.\n", dlatch->name.c_str(), dlatch->type.c_str(), mod->name.c_str());
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mod->remove(dlatch);
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return true;
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}
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bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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{
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RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r;
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@ -178,6 +205,7 @@ struct OptRmdffPass : public Pass {
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mux_drivers.clear();
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std::vector<RTLIL::IdString> dff_list;
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std::vector<RTLIL::IdString> dlatch_list;
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for (auto &it : mod_it.second->cells_) {
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if (it.second->type == "$mux" || it.second->type == "$pmux") {
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if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size())
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@ -198,6 +226,7 @@ struct OptRmdffPass : public Pass {
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if (it.second->type == "$_DFF_PP1_") dff_list.push_back(it.first);
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if (it.second->type == "$dff") dff_list.push_back(it.first);
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if (it.second->type == "$adff") dff_list.push_back(it.first);
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if (it.second->type == "$dlatch") dlatch_list.push_back(it.first);
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}
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for (auto &id : dff_list) {
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@ -205,6 +234,12 @@ struct OptRmdffPass : public Pass {
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handle_dff(mod_it.second, mod_it.second->cells_[id]))
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total_count++;
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}
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for (auto &id : dlatch_list) {
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if (mod_it.second->cells_.count(id) > 0 &&
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handle_dlatch(mod_it.second, mod_it.second->cells_[id]))
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total_count++;
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}
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}
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assign_map.clear();
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