mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
memory_dff: Fix checking of feedback mux input when more than one mux
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7b298479d4
commit
4b49c0201e
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@ -17,6 +17,7 @@
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*
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*
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*/
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*/
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#include <algorithm>
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#include "kernel/yosys.h"
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/sigtools.h"
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@ -183,12 +184,12 @@ struct MemoryDffWorker
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if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
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if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
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{
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{
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RTLIL::SigSpec en;
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RTLIL::SigSpec en;
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RTLIL::SigSpec check_q;
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std::vector<RTLIL::SigSpec> check_q;
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do {
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do {
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bool enable_invert = mux_cells_a.count(sig_data) != 0;
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bool enable_invert = mux_cells_a.count(sig_data) != 0;
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Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
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Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
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check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
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check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
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sig_data = sigmap(mux->getPort("\\Y"));
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sig_data = sigmap(mux->getPort("\\Y"));
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en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
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en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
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} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
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} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
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@ -197,7 +198,8 @@ struct MemoryDffWorker
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if (sigbit_users_count[bit] > 1)
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if (sigbit_users_count[bit] > 1)
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goto skip_ff_after_read_merging;
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goto skip_ff_after_read_merging;
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if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
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if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
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std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
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{
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{
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disconnect_dff(sig_data);
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disconnect_dff(sig_data);
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cell->setPort("\\CLK", clk_data);
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cell->setPort("\\CLK", clk_data);
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@ -0,0 +1,16 @@
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// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-no-rd-clk
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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reg [7:0] bram[0:255];
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(* keep *) reg dummy;
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always @(posedge clk) begin
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rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
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if (we)
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bram[addr] <= wdata;
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end
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endmodule
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@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
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grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
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{ echo " ERROR: Unexpected read clock."; false; }
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{ echo " ERROR: Unexpected read clock."; false; }
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fi
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fi
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if grep -q expect-no-rd-clk $f; then
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grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
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{ echo " ERROR: Expected no read clock."; false; }
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fi
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echo " ok."
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echo " ok."
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done
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done
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