mirror of https://github.com/YosysHQ/yosys.git
Further improved and extended xsthammer
This commit is contained in:
Clifford Wolf
parent
8ce99fa686
commit
4b311b7b99
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@ -234,6 +234,7 @@ supply1 { return TOK_SUPPLY1; }
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">=" { return OP_GE; }
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"===" { return OP_EQ; }
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"!==" { return OP_NE; }
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/* "~&" { return OP_NAND; } */
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/* "~|" { return OP_NOR; } */
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@ -1,4 +1,5 @@
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generate
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generate.lst
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rtl
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xst
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xst_temp
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@ -0,0 +1,28 @@
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include generate.lst
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test: $(TARGETS)
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check/%.log: rtl/%.v xst/%.v
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bash run-check.sh $(notdir $(basename $<))
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xst/%.v: rtl/%.v
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bash run-xst.sh $(notdir $(basename $<))
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generate.lst: generate.cc
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clang -Wall -o generate generate.cc -lstdc++
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./generate
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{ echo -n "TARGETS := "; ls rtl/ | sed 's,\.v$$,.log,; s,^,check/,;' | tr '\n' ' '; } > generate.lst
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check_xl_cells:
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../../yosys xl_cells_tb.ys
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clean:
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rm -rf generate generate.lst check_temp xst_temp
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mrproper: clean
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rm -rf rtl xst check
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.PHONY: test check_xl_cells clean mrproper
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.PRECIOUS: check/%.log xst/%.v rtl/%.v generate.lst
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@ -9,15 +9,6 @@ to synthesize them with Yosys and Xilinx XST and perform formal equivialence
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checks using the Yosys SAT-based equivialence checker. This will hopefully
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reveal some bugs in both applications.. ;-)
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Generating the Test Cases:
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clang -Wall -o generate generate.cc -lstdc++
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./generate
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Running XST Synthesis:
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bash run-xst.sh
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rm -rf xst_temp
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Running Yosys Synthesis and Check:
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TBD
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Simply run 'make' to generate all test cases and run all the tests.
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(Use 'make -j N' to use N parallel cores.)
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@ -13,19 +13,47 @@ const char *arg_types[][2] = {
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{ "{dir} signed [5:0] {name}", "{name}" } // 05
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};
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const char *ops[] = {
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// See Table 5-1 (page 42) in IEEE Std 1364-2005
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// for a list of all Verilog oprators.
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const char *binary_ops[] = {
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"+", // 00
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"-", // 01
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"*", // 02
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"&&", // 03
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"||", // 04
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"&", // 05
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// "/",
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// "%",
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// "**",
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">", // 03
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">=", // 04
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"<", // 05
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"<=", // 06
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"&&", // 07
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"||", // 08
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"==", // 09
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"!=", // 10
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"===", // 11
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"!==", // 12
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"&", // 13
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"|", // 14
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"^", // 15
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"^~", // 16
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"<<", // 17
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">>", // 18
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"<<<", // 19
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">>>", // 20
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};
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const char *unary_ops[] = {
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"+", // 00
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"-", // 01
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"!", // 02
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"~", // 03
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"&", // 04
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"~&", // 05
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"|", // 06
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"^", // 07
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"<<", // 08
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">>", // 09
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"<<<", // 10
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">>>", // 11
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"~|", // 07
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"^", // 08
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"~^", // 09
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};
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void strsubst(std::string &str, const std::string &match, const std::string &replace)
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@ -38,10 +66,13 @@ void strsubst(std::string &str, const std::string &match, const std::string &rep
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int main()
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{
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mkdir("rtl", 0777);
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// generate test cases for binary operators
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for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
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for (int bi = 0; bi < sizeof(arg_types)/sizeof(arg_types[0]); bi++)
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for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
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for (int oi = 0; oi < sizeof(ops)/sizeof(ops[0]); oi++)
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for (int oi = 0; oi < sizeof(binary_ops)/sizeof(binary_ops[0]); oi++)
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{
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std::string a_decl = arg_types[ai][0];
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strsubst(a_decl, "{dir}", "input");
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@ -76,10 +107,46 @@ int main()
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fprintf(f, "%s;\n", b_decl.c_str());
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fprintf(f, "%s;\n", y_decl.c_str());
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fprintf(f, "assign %s = %s %s %s;\n", y_ref.c_str(),
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a_ref.c_str(), ops[oi], b_ref.c_str());
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a_ref.c_str(), binary_ops[oi], b_ref.c_str());
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fprintf(f, "endmodule\n");
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fclose(f);
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}
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// generate test cases for unary operators
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for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
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for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
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for (int oi = 0; oi < sizeof(unary_ops)/sizeof(unary_ops[0]); oi++)
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{
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std::string a_decl = arg_types[ai][0];
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strsubst(a_decl, "{dir}", "input");
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strsubst(a_decl, "{name}", "a");
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std::string y_decl = arg_types[yi][0];
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strsubst(y_decl, "{dir}", "output");
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strsubst(y_decl, "{name}", "y");
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std::string a_ref = arg_types[ai][1];
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strsubst(a_ref, "{dir}", "input");
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strsubst(a_ref, "{name}", "a");
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std::string y_ref = arg_types[yi][1];
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strsubst(y_ref, "{dir}", "output");
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strsubst(y_ref, "{name}", "y");
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char buffer[1024];
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snprintf(buffer, 1024, "rtl/unary_ops_%02d%02d%02d.v", ai, yi, oi);
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FILE *f = fopen(buffer, "w");
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fprintf(f, "module unary_ops_%02d%02d%02d(a, b, y);\n", ai, yi, oi);
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fprintf(f, "%s;\n", a_decl.c_str());
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fprintf(f, "%s;\n", y_decl.c_str());
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fprintf(f, "assign %s = %s %s;\n", y_ref.c_str(),
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unary_ops[oi], a_ref.c_str());
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fprintf(f, "endmodule\n");
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fclose(f);
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}
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return 0;
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}
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@ -1,65 +1,65 @@
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#!/bin/bash
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set -e
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mkdir -p check
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rm -rf check_temp
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mkdir check_temp
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cd check_temp
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if [ $# -eq 0 ]; then
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set -- $( ls ../rtl | sed 's,\.v$,,' )
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echo "Usage: $0 <job_id>" >&2
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exit 1
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fi
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for job
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do
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job="$1"
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set --
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set -e
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mkdir -p check check_temp
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cd check_temp
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{
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echo "module ${job}_top(a, b, y_rtl, y_xst);"
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sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_xst;/;' ../rtl/$job.v
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echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y_rtl));"
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echo "${job}_xst xst_variant (.a(a), .b(b), .y(y_xst));"
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echo "endmodule"
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} > ${job}_top.v
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for mode in nomap techmap; do
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{
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echo "module ${job}_top(a, b, y_rtl, y_xst);"
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sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_xst;/;' ../rtl/$job.v
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echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y_rtl));"
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echo "${job}_xst xst_variant (.a(a), .b(b), .y(y_xst));"
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echo "endmodule"
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} > ${job}_top.v
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echo "read_verilog -DGLBL ../xst/$job.v"
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echo "rename $job ${job}_xst"
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for mode in nomap techmap; do
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{
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echo "read_verilog -DGLBL ../xst/$job.v"
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echo "rename $job ${job}_xst"
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echo "read_verilog ../rtl/$job.v"
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echo "rename $job ${job}_rtl"
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if [ $mode = techmap ]; then
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echo "techmap ${job}_rtl"
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fi
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echo "read_verilog ../rtl/$job.v"
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echo "rename $job ${job}_rtl"
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if [ $mode = techmap ]; then
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echo "techmap ${job}_rtl"
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fi
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echo "read_verilog ${job}_top.v"
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echo "read_verilog ../xl_cells.v"
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echo "read_verilog ${job}_top.v"
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echo "read_verilog ../xl_cells.v"
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echo "hierarchy -top ${job}_top"
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echo "flatten ${job}_top"
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echo "hierarchy -top ${job}_top"
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echo "opt_clean"
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echo "hierarchy -top ${job}_top"
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echo "flatten ${job}_top"
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echo "hierarchy -top ${job}_top"
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echo "opt_clean"
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echo "rename ${job}_top ${job}_top_${mode}"
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echo "write_ilang ${job}_top_${mode}.il"
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} > ${job}_top_${mode}.ys
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../../../yosys -q ${job}_top_${mode}.ys
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done
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{
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echo "read_ilang ${job}_top_nomap.il"
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echo "read_ilang ${job}_top_techmap.il"
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echo "sat -verify -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_nomap"
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echo "sat -verify -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_techmap"
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} > ${job}_cmp.ys
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if ../../../yosys -l ${job}.log ${job}_cmp.ys; then
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mv ${job}.log ../check/${job}.log
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rm -f ../check/${job}.err
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else
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mv ${job}.log ../check/${job}.err
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rm -f ../check/${job}.log
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# break
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fi
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echo "rename ${job}_top ${job}_top_${mode}"
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echo "write_ilang ${job}_top_${mode}.il"
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} > ${job}_top_${mode}.ys
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../../../yosys -q ${job}_top_${mode}.ys
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done
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{
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echo "read_ilang ${job}_top_nomap.il"
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echo "read_ilang ${job}_top_techmap.il"
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echo "sat -verify -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_nomap"
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echo "sat -verify -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_techmap"
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} > ${job}_cmp.ys
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if ../../../yosys -l ${job}.log ${job}_cmp.ys; then
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mv ${job}.log ../check/${job}.log
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rm -f ../check/${job}.err
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else
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mv ${job}.log ../check/${job}.err
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rm -f ../check/${job}.log
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exit 1
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fi
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exit 0
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@ -1,75 +1,76 @@
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#!/bin/bash
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set -e
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mkdir -p xst
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. /opt/Xilinx/14.2/ISE_DS/settings64.sh
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rm -rf xst_temp
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mkdir xst_temp
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cd xst_temp
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if [ $# -eq 0 ]; then
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set -- $( ls ../rtl | sed 's,\.v$,,' )
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echo "Usage: $0 <job_id>" >&2
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exit 1
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fi
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for job
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do
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cat > $job.xst <<- EOT
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run
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-ifn $job.prj
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-ifmt mixed
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-ofn $job
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-ofmt NGC
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-p xc6vlx75t-2-ff784
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-top $job
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-keep_hierarchy NO
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-shreg_extract YES
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-rom_style Auto
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-auto_bram_packing NO
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf NO
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-max_fanout 100000
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-bufg 32
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-register_duplication YES
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-register_balancing No
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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EOT
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job="$1"
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set --
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cat > $job.prj <<- EOT
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verilog work "../rtl/$job.v"
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EOT
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set -e
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mkdir -p xst xst_temp/$job
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cd xst_temp/$job
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xst -ifn $job.xst
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netgen -w -ofmt verilog $job.ngc $job
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cp $job.v ../xst/$job.v
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done
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cat > $job.xst <<- EOT
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run
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-ifn $job.prj
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-ifmt mixed
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-ofn $job
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-ofmt NGC
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-p xc6vlx75t-2-ff784
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-top $job
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-keep_hierarchy NO
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style lut
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-shreg_extract YES
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-rom_style Auto
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-auto_bram_packing NO
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-resource_sharing YES
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-async_to_sync NO
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-use_dsp48 auto
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-iobuf NO
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-max_fanout 100000
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-bufg 32
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-register_duplication YES
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-register_balancing No
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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EOT
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cat > $job.prj <<- EOT
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verilog work "../../rtl/$job.v"
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EOT
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. /opt/Xilinx/14.2/ISE_DS/settings64.sh
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xst -ifn $job.xst
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netgen -w -ofmt verilog $job.ngc $job
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cp $job.v ../../xst/$job.v
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exit 0
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