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Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 

opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
This commit is contained in:
Eddie Hung 2020-04-01 14:17:01 -07:00 committed by GitHub
parent e79bc45975 0c0dc4ffc3
commit 4ae7f3a8ed
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 92 additions and 10 deletions
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40
passes/opt/opt_expr.cc
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@ -496,6 +496,42 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
} }
if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()))
{
SigBit sig_a = assign_map(cell->getPort(ID::A));
SigBit sig_b = assign_map(cell->getPort(ID::B));
if (!sig_a.wire)
std::swap(sig_a, sig_b);
if (sig_b == State::S0 || sig_b == State::S1) {
if (cell->type.in(ID($xor), ID($_XOR_))) {
cover("opt.opt_expr.xor_buffer");
SigSpec sig_y;
if (cell->type == ID($xor))
sig_y = (sig_b == State::S1 ? module->Not(NEW_ID, sig_a).as_bit() : sig_a);
else if (cell->type == ID($_XOR_))
sig_y = (sig_b == State::S1 ? module->NotGate(NEW_ID, sig_a) : sig_a);
else log_abort();
replace_cell(assign_map, module, cell, "xor_buffer", ID::Y, sig_y);
goto next_cell;
}
if (cell->type.in(ID($xnor), ID($_XNOR_))) {
cover("opt.opt_expr.xnor_buffer");
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
int width = cell->getParam(ID(Y_WIDTH)).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
sig_y = (sig_b == State::S1 ? sig_a : module->NotGate(NEW_ID, sig_a));
else log_abort();
replace_cell(assign_map, module, cell, "xnor_buffer", ID::Y, sig_y);
goto next_cell;
}
log_abort();
}
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) && if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor), ID($neg)) &&
GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1) GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
{ {
@ -850,8 +886,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (input.match("11")) ACTION_DO_Y(0); if (input.match("11")) ACTION_DO_Y(0);
if (input.match(" *")) ACTION_DO_Y(x); if (input.match(" *")) ACTION_DO_Y(x);
if (input.match("* ")) ACTION_DO_Y(x); if (input.match("* ")) ACTION_DO_Y(x);
if (input.match(" 0")) ACTION_DO(ID::Y, input.extract(1, 1));
if (input.match("0 ")) ACTION_DO(ID::Y, input.extract(0, 1));
} }
if (cell->type == ID($_MUX_)) { if (cell->type == ID($_MUX_)) {
@ -1622,7 +1656,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
int const_bit_set = get_highest_hot_index(const_sig); int const_bit_set = get_highest_hot_index(const_sig);
if(const_bit_set >= var_width) if (const_bit_set >= var_width)
{ {
string cmp_name; string cmp_name;
if (cmp_type == ID($lt) || cmp_type == ID($le)) if (cmp_type == ID($lt) || cmp_type == ID($le))

5
tests/arch/anlogic/fsm.ys
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@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT2
select -assert-count 5 t:AL_MAP_LUT5
select -assert-count 1 t:AL_MAP_LUT6
select -assert-count 6 t:AL_MAP_SEQ select -assert-count 6 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D

5
tests/arch/efinix/fsm.ys
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@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF select -assert-count 6 t:EFX_FF
select -assert-count 15 t:EFX_LUT4
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D

52
tests/opt/opt_expr_xor.ys Normal file
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@ -0,0 +1,52 @@
read_verilog <<EOT
module top(input a, output [3:0] y);
assign y[0] = a^1'b0;
assign y[1] = 1'b1^a;
assign y[2] = a~^1'b0;
assign y[3] = 1'b1^~a;
endmodule
EOT
design -save read
select -assert-count 2 t:$xor
select -assert-count 2 t:$xnor
equiv_opt opt_expr
design -load postopt
select -assert-none t:$xor
select -assert-none t:$xnor
select -assert-count 2 t:$not
design -load read
simplemap
equiv_opt opt_expr
design -load postopt
select -assert-none t:$_XOR_
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
select -assert-count 3 t:$_NOT_
design -reset
read_verilog -icells <<EOT
module top(input a, output [1:0] y);
$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
endmodule
EOT
select -assert-count 2 t:$_XNOR_
equiv_opt opt_expr
design -load postopt
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
select -assert-count 1 t:$_NOT_
design -reset
read_verilog <<EOT
module top(input a, output [1:0] w, x, y, z);
assign w = a^1'b0;
assign x = a^1'b1;
assign y = a~^1'b0;
assign z = a~^1'b1;
endmodule
EOT
equiv_opt opt_expr