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Fixed a type in $mem model in simlib.v

This commit is contained in:
Clifford Wolf 2014-01-18 18:54:50 +01:00
parent bef17eeb10
commit 4a9e133fab
1 changed files with 1 additions and 1 deletions
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2
techlibs/common/simlib.v
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@ -1036,7 +1036,7 @@ generate
end end
end end
end else end else
if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
always @(posedge WR_CLK[i]) always @(posedge WR_CLK[i])
if (WR_EN[i]) begin if (WR_EN[i]) begin
data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ]; data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];