diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index c3bb1933a..dfd025a51 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -43,11 +43,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 
 	assign_map.apply(sig);
 	if (sig.is_fully_const()) {
-		sig.optimize();
-		assert(sig.chunks().size() == 1);
-		if (states.count(sig.chunks()[0].data) == 0) {
+		if (states.count(sig.as_const()) == 0) {
 			log("  found state code: %s\n", log_signal(sig));
-			states[sig.chunks()[0].data] = -1;
+			states[sig.as_const()] = -1;
 		}
 		return true;
 	}
@@ -91,30 +89,19 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
 {
 	if (dont_care.size() > 0) {
-		sig.expand();
-		for (auto &chunk : sig.chunks_rw()) {
-			assert(chunk.width == 1);
-			if (dont_care.extract(chunk).size() > 0)
-				chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
-		}
-		sig.optimize();
+		for (int i = 0; i < SIZE(sig); i++)
+			if (dont_care.extract(sig[i]).size() > 0)
+				sig[i] = noconst_state;
 	}
 
 	ce.assign_map.apply(sig);
 	ce.values_map.apply(sig);
 
-	sig.expand();
-	for (auto &chunk : sig.chunks_rw()) {
-		assert(chunk.width == 1);
-		if (chunk.wire != NULL)
-			chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
-	}
-	sig.optimize();
+	for (int i = 0; i < SIZE(sig); i++)
+		if (sig[i].wire != NULL)
+			sig[i] = noconst_state;
 
-	if (sig.size() == 0)
-		return RTLIL::Const();
-	assert(sig.chunks().size() == 1 && sig.chunks()[0].wire == NULL);
-	return sig.chunks()[0].data;
+	return sig.as_const();
 }
 
 static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care)
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index d5a9b71fa..efa61245a 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -33,18 +33,14 @@ struct FsmOpt
 	
 	bool signal_is_unused(RTLIL::SigSpec sig)
 	{
-		assert(sig.size() == 1);
-		sig.optimize();
+		RTLIL::SigBit bit = sig.to_single_sigbit();
 
-		RTLIL::Wire *wire = sig.chunks()[0].wire;
-		int bit = sig.chunks()[0].offset;
-
-		if (!wire || wire->attributes.count("\\unused_bits") == 0)
+		if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
 			return false;
 		
-		char *str = strdup(wire->attributes["\\unused_bits"].decode_string().c_str());
+		char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
 		for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
-			if (tok[0] && bit == atoi(tok)) {
+			if (tok[0] && bit.offset == atoi(tok)) {
 				free(str);
 				return true;
 			}
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 718b97043..d0be71c5b 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -142,26 +142,24 @@ struct FsmData
 		log("\n");
 		log("  Input signals:\n");
 		RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
-		sig_in.expand();
-		for (size_t i = 0; i < sig_in.chunks().size(); i++)
-			log("  %3zd: %s\n", i, log_signal(sig_in.chunks()[i]));
+		for (int i = 0; i < SIZE(sig_in); i++)
+			log("  %3zd: %s\n", i, log_signal(sig_in[i]));
 
 		log("\n");
 		log("  Output signals:\n");
 		RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
-		sig_out.expand();
-		for (size_t i = 0; i < sig_out.chunks().size(); i++)
-			log("  %3zd: %s\n", i, log_signal(sig_out.chunks()[i]));
+		for (int i = 0; i < SIZE(sig_out); i++)
+			log("  %3zd: %s\n", i, log_signal(sig_out[i]));
 
 		log("\n");
 		log("  State encoding:\n");
-		for (size_t i = 0; i < state_table.size(); i++)
+		for (int i = 0; i < SIZE(state_table); i++)
 			log("  %3zd: %10s%s\n", i, log_signal(state_table[i], false),
 					int(i) == reset_state ? "  <RESET STATE>" : "");
 
 		log("\n");
 		log("  Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
-		for (size_t i = 0; i < transition_table.size(); i++) {
+		for (int i = 0; i < SIZE(transition_table); i++) {
 			transition_t &tr = transition_table[i];
 			log("  %5zd: %5d %s   -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
 		}