Ignore explicit unconnected ports in intersynth backend

This commit is contained in:
Clifford Wolf 2013-11-03 09:00:51 +01:00
parent d78a9dfb37
commit 4a60e5842d
1 changed files with 5 additions and 3 deletions
backends/intersynth

View File

@ -174,10 +174,12 @@ struct IntersynthBackend : public Backend {
node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
for (auto &port : cell->connections) { for (auto &port : cell->connections) {
RTLIL::SigSpec sig = sigmap(port.second); RTLIL::SigSpec sig = sigmap(port.second);
if (sig.width != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width)); conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.width, sig.width, sig.width));
celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first)); celltype_code += stringf(" b%d %s%s", sig.width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
} }
}
for (auto &param : cell->parameters) { for (auto &param : cell->parameters) {
celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first)); celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), RTLIL::id2cstr(param.first));
if (param.second.bits.size() != 32) { if (param.second.bits.size() != 32) {