mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: include iostream when prints are used
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cbd3ff2d3a
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4a475fa7a2
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@ -2474,6 +2474,7 @@ struct CxxrtlWorker {
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RTLIL::Module *top_module = nullptr;
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RTLIL::Module *top_module = nullptr;
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std::vector<RTLIL::Module*> modules;
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std::vector<RTLIL::Module*> modules;
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TopoSort<RTLIL::Module*> topo_design;
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TopoSort<RTLIL::Module*> topo_design;
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bool has_prints = false;
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for (auto module : design->modules()) {
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for (auto module : design->modules()) {
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if (!design->selected_module(module))
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if (!design->selected_module(module))
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continue;
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continue;
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@ -2486,6 +2487,8 @@ struct CxxrtlWorker {
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topo_design.node(module);
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topo_design.node(module);
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for (auto cell : module->cells()) {
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for (auto cell : module->cells()) {
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if (cell->type == ID($print))
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has_prints = true;
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if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
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if (is_internal_cell(cell->type) || is_cxxrtl_blackbox_cell(cell))
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continue;
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continue;
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RTLIL::Module *cell_module = design->module(cell->type);
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RTLIL::Module *cell_module = design->module(cell->type);
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@ -2544,6 +2547,8 @@ struct CxxrtlWorker {
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f << "#include \"" << intf_filename << "\"\n";
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f << "#include \"" << intf_filename << "\"\n";
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else
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else
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f << "#include <backends/cxxrtl/cxxrtl.h>\n";
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f << "#include <backends/cxxrtl/cxxrtl.h>\n";
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if (has_prints)
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f << "#include <iostream>\n";
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f << "\n";
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f << "\n";
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f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
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f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
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f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
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f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
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@ -1,4 +1,3 @@
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#include <iostream>
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#include "yosys-always_comb.cc"
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#include "yosys-always_comb.cc"
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int main()
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int main()
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@ -1,4 +1,3 @@
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#include <iostream>
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#include "yosys-always_full.cc"
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#include "yosys-always_full.cc"
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int main()
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int main()
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@ -1,4 +1,3 @@
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#include <iostream>
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#include "yosys-display_lm.cc"
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#include "yosys-display_lm.cc"
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int main()
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int main()
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