diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 5554ae31b..e15bc0fc8 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -1 +1 @@
-test_ffs_[01][01][01][01]_*
+test_ffs_[01][01][01][01][01]_*
diff --git a/techlibs/ice40/tests/test_ffs.sh b/techlibs/ice40/tests/test_ffs.sh
index 5affcbdd9..ff79ec534 100644
--- a/techlibs/ice40/tests/test_ffs.sh
+++ b/techlibs/ice40/tests/test_ffs.sh
@@ -4,10 +4,11 @@ for CLKPOL in 0 1; do
 for ENABLE_EN in 0 1; do
 for RESET_EN in 0 1; do
 for RESET_VAL in 0 1; do
-	pf="test_ffs_${CLKPOL}${ENABLE_EN}${RESET_EN}${RESET_VAL}"
+for RESET_SYN in 0 1; do
+	pf="test_ffs_${CLKPOL}${ENABLE_EN}${RESET_EN}${RESET_VAL}${RESET_SYN}"
 	sed -e "s/CLKPOL = 0/CLKPOL = ${CLKPOL}/;" -e "s/ENABLE_EN = 0/ENABLE_EN = ${ENABLE_EN}/;" \
 	    -e "s/RESET_EN = 0/RESET_EN = ${RESET_EN}/;" -e "s/RESET_VAL = 0/RESET_VAL = ${RESET_VAL}/;" \
-	    test_ffs.v > ${pf}_gold.v
+	    -e "s/RESET_SYN = 0/RESET_SYN = ${RESET_SYN}/;" test_ffs.v > ${pf}_gold.v
 	../../../yosys -o ${pf}_gate.v -p "synth_ice40" ${pf}_gold.v
 	../../../yosys -p "proc; opt; test_autotb ${pf}_tb.v" ${pf}_gold.v
 	iverilog -s testbench -o ${pf}_gold ${pf}_gold.v ${pf}_tb.v
@@ -15,5 +16,5 @@ for RESET_VAL in 0 1; do
 	./${pf}_gold > ${pf}_gold.txt
 	./${pf}_gate > ${pf}_gate.txt
 	cmp ${pf}_gold.txt ${pf}_gate.txt
-done; done; done; done
+done; done; done; done; done
 echo OK.
diff --git a/techlibs/ice40/tests/test_ffs.v b/techlibs/ice40/tests/test_ffs.v
index 3bef59fb3..1f6883f3c 100644
--- a/techlibs/ice40/tests/test_ffs.v
+++ b/techlibs/ice40/tests/test_ffs.v
@@ -3,6 +3,7 @@ module test(D, C, E, R, Q);
 	parameter [0:0] ENABLE_EN = 0;
 	parameter [0:0] RESET_EN = 0;
 	parameter [0:0] RESET_VAL = 0;
+	parameter [0:0] RESET_SYN = 0;
 
 	(* gentb_clock *)
 	input D, C, E, R;
@@ -11,7 +12,7 @@ module test(D, C, E, R, Q);
 
 	wire gated_reset = R & RESET_EN;
 	wire gated_enable = E | ~ENABLE_EN;
-	reg posedge_q, negedge_q;
+	reg posedge_q, negedge_q, posedge_sq, negedge_sq;
 
 	always @(posedge C, posedge gated_reset)
 		if (gated_reset)
@@ -25,5 +26,17 @@ module test(D, C, E, R, Q);
 		else if (gated_enable)
 			negedge_q <= D;
 
-	assign Q = CLKPOL ? posedge_q : negedge_q;
+	always @(posedge C)
+		if (gated_reset)
+			posedge_sq <= RESET_VAL;
+		else if (gated_enable)
+			posedge_sq <= D;
+
+	always @(negedge C)
+		if (gated_reset)
+			negedge_sq <= RESET_VAL;
+		else if (gated_enable)
+			negedge_sq <= D;
+
+	assign Q = RESET_SYN ? (CLKPOL ? posedge_sq : negedge_sq) : (CLKPOL ? posedge_q : negedge_q);
 endmodule