mirror of https://github.com/YosysHQ/yosys.git
write_xaiger: fix arrival times for non boxes
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parent
509070f82f
commit
49881b4468
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@ -250,29 +250,30 @@ struct XAigerWriter
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}
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}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module && inst_module->attributes.count("\\abc9_box_id")) {
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if (inst_module) {
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abc9_box_seen = true;
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_input) {
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int arrival = 0;
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_output) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (port_wire->port_output) {
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if (port_wire->port_output) {
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int arrival = 0;
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auto it = port_wire->attributes.find("\\abc9_arrival");
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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arrival = it->second.as_int();
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}
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}
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}
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if (abc9_box) {
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if (port_wire->port_input) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_output) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second)) {
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for (auto bit : sigmap(conn.second)) {
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bit_drivers[bit].insert(cell->name);
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bit_drivers[bit].insert(cell->name);
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if (arrival)
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if (arrival)
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@ -282,10 +283,16 @@ struct XAigerWriter
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}
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}
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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if (inst_module->attributes.count("\\abc9_flop"))
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if (inst_module->attributes.count("\\abc9_flop"))
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flop_boxes.push_back(cell);
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flop_boxes.push_back(cell);
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continue;
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continue;
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}
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}
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}
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bool cell_known = inst_module || cell->known();
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bool cell_known = inst_module || cell->known();
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for (const auto &c : cell->connections()) {
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for (const auto &c : cell->connections()) {
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