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Added "synth_ice40 -abc2"

This commit is contained in:
Clifford Wolf 2015-12-08 11:16:26 +01:00
parent 4d0a6dac7b
commit 494e5f24f9
1 changed files with 11 additions and 0 deletions
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11
techlibs/ice40/synth_ice40.cc
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@ -72,6 +72,9 @@ struct SynthIce40Pass : public Pass {
log(" -nobram\n"); log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n"); log(" do not use SB_RAM40_4K* cells in output netlist\n");
log("\n"); log("\n");
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
log("\n"); log("\n");
@ -109,6 +112,7 @@ struct SynthIce40Pass : public Pass {
log(" ice40_opt -full\n"); log(" ice40_opt -full\n");
log("\n"); log("\n");
log(" map_luts:\n"); log(" map_luts:\n");
log(" abc (only if -abc2)\n");
log(" abc -lut 4\n"); log(" abc -lut 4\n");
log(" clean\n"); log(" clean\n");
log("\n"); log("\n");
@ -137,6 +141,7 @@ struct SynthIce40Pass : public Pass {
bool nobram = false; bool nobram = false;
bool flatten = true; bool flatten = true;
bool retime = false; bool retime = false;
bool abc2 = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
@ -181,6 +186,10 @@ struct SynthIce40Pass : public Pass {
nobram = true; nobram = true;
continue; continue;
} }
if (args[argidx] == "-abc2") {
abc2 = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -244,6 +253,8 @@ struct SynthIce40Pass : public Pass {
if (check_label(active, run_from, run_to, "map_luts")) if (check_label(active, run_from, run_to, "map_luts"))
{ {
if (abc2)
Pass::call(design, "abc");
Pass::call(design, "abc -lut 4"); Pass::call(design, "abc -lut 4");
Pass::call(design, "clean"); Pass::call(design, "clean");
} }