mirror of https://github.com/YosysHQ/yosys.git
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
This commit is contained in:
Andrew Zonenberg
parent
3ea6026648
commit
489caf32c5
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@ -25,6 +25,7 @@ OBJS += passes/techmap/aigmap.o
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OBJS += passes/techmap/tribuf.o
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OBJS += passes/techmap/lut2mux.o
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OBJS += passes/techmap/nlutmap.o
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OBJS += passes/techmap/counters.o
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OBJS += passes/techmap/dffsr2dff.o
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endif
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@ -0,0 +1,220 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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//get the list of cells hooked up to at least one bit of a given net
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std::set<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
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{
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std::set<Cell*> rval;
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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if(x.cell == src)
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continue;
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rval.insert(x.cell);
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}
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}
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return rval;
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}
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//return true if there is a full-width bus connection between the two named module/port combos
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bool is_full_bus(const RTLIL::SigSpec& sig, ModIndex& index, Cell* a, RTLIL::IdString ap, Cell* b, RTLIL::IdString bp)
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{
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for(auto s : sig)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(s);
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bool found_a = false;
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bool found_b = false;
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for(auto x : ports)
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{
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if( (x.cell == a) && (x.port == ap) )
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found_a = true;
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else if( (x.cell == b) && (x.port == bp) )
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found_b = true;
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else
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return false;
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}
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if( (!found_a) || (!found_b) )
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return false;
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}
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return true;
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}
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//return true if the signal connects to one port only (nothing on the other end)
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bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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{
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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if(ports.size() > 1)
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return false;
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}
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return true;
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}
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void counters_worker(SigMap &sigmap, Module *module, Cell *cell)
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{
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if (cell->type == "$alu")
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{
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//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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if(a_width > 14)
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return;
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//Second input must be a single bit
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if(b_width != 1)
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return;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
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bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
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if(a_sign || b_sign)
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return;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return;
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//Index the module
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ModIndex index(module);
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//We found a decrementer. Not sure if it's a counter yet but log for debugging
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log(" Found candidate counter %s (width %d)\n", cell->name.c_str(), a_width);
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
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return;
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if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
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return;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
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std::set<Cell*> y_loads = get_other_cells(aluy, index, cell);
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if(y_loads.size() != 1)
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return;
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Cell* count_mux = *y_loads.begin();
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if(count_mux->type != "$mux")
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return;
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if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
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return;
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//B connection of the mux is our overflow value
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const RTLIL::SigSpec overflow = sigmap(count_mux->getPort("\\B"));
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if(!overflow.is_fully_const())
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return;
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int count_value = overflow.as_int();
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//TODO: S connection of the mux must come from an inverter
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//Y connection of the mux must have exactly one load, the counter's internal register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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std::set<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return;
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Cell* count_reg = *muxy_loads.begin();
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if(count_reg->type != "$dff") //TODO: support dffr/dffs?
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return;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return;
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log(" Looks like a counter so far (count value = %d, count_reg = %s)\n",
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count_value, count_reg->name.c_str());
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/*
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log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
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if (GetSize(setctrl) == 1) {
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cell->setPort("\\ARST", setctrl);
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cell->setParam("\\ARST_POLARITY", setpol);
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} else {
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cell->setPort("\\ARST", clrctrl);
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cell->setParam("\\ARST_POLARITY", clrpol);
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}
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cell->type = "$adff";
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cell->unsetPort("\\SET");
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cell->unsetPort("\\CLR");
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cell->setParam("\\ARST_VALUE", reset_val);
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cell->unsetParam("\\SET_POLARITY");
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cell->unsetParam("\\CLR_POLARITY");
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return;
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*/
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}
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}
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struct CountersPass : public Pass {
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CountersPass() : Pass("counters", "Extract counter cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" counters [options] [selection]\n");
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log("\n");
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log("This pass converts resettable down counters to GreenPak counter cells\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing COUNTERS pass (mapping counters to GP_COUNTx cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-v") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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counters_worker(sigmap, module, cell);
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}
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}
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} CountersPass;
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PRIVATE_NAMESPACE_END
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@ -92,6 +92,33 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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//more complex hard IP blocks are not supported for simulation yet
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reg[7:0] count = COUNT_TO;
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//Combinatorially output whenever we wrap low
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always @(*) begin
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OUT <= (count == 8'h0);
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end
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//datasheet is unclear but experimental testing confirms that POR value is COUNT_TO.
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//Reset value is clearly 0 except in count/FSM cells where it's configurable.
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//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
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always @(posedge CLK) begin
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count <= count - 1'd1;
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if(count == 0)
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count <= COUNT_MAX;
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/*
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if((RESET_MODE == "RISING") && RST)
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count <= 0;
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if((RESET_MODE == "FALLING") && !RST)
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count <= 0;
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if((RESET_MODE == "BITH") && RST)
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count <= 0;
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*/
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end
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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