mirror of https://github.com/YosysHQ/yosys.git
Liberty file parser now accepts superfluous ;
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parent
7682629b79
commit
487cb45b87
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@ -158,8 +158,10 @@ int LibertyParser::lexer(std::string &str)
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c = f.get();
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if (c == '\r')
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c = f.get();
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if (c == '\n')
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if (c == '\n') {
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line++;
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return lexer(str);
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}
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f.unget();
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return '\\';
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}
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@ -186,14 +188,39 @@ LibertyAst *LibertyParser::parse()
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int tok = lexer(str);
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while (tok == 'n')
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// there are liberty files in the while that
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// have superfluous ';' at the end of
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// a { ... }. We simply ignore a ';' here.
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// and get to the next statement.
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while ((tok == 'n') || (tok == ';'))
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tok = lexer(str);
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if (tok == '}' || tok < 0)
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return NULL;
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if (tok != 'v')
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error();
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if (tok != 'v') {
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std::string eReport;
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switch(tok)
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{
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case 'n':
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error("Unexpected newline.");
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break;
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case '[':
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case ']':
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case '}':
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case '{':
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case '\"':
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case ':':
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eReport = "Unexpected '";
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eReport += static_cast<char>(tok);
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eReport += "'.";
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error(eReport);
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break;
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default:
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error();
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}
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}
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LibertyAst *ast = new LibertyAst;
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ast->id = str;
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@ -282,8 +309,28 @@ LibertyAst *LibertyParser::parse()
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}
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continue;
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}
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if (tok != 'v')
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error();
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if (tok != 'v') {
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std::string eReport;
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switch(tok)
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{
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case 'n':
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error("Unexpected newline.");
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break;
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case '[':
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case ']':
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case '}':
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case '{':
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case '\"':
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case ':':
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eReport = "Unexpected '";
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eReport += static_cast<char>(tok);
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eReport += "'.";
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error(eReport);
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break;
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default:
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error();
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}
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}
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ast->args.push_back(arg);
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}
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continue;
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@ -142,8 +142,7 @@ library(supergate) {
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}
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/* D-type flip-flop with asynchronous reset and preset */
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cell (dff)
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{
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cell (dff) {
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area : 6;
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ff("IQ", "IQN") {
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next_state : "D";
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@ -0,0 +1,48 @@
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/********************************************/
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/* */
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/* Supergate cell library for Bench marking */
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/* */
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/* Symbiotic EDA GmbH / Moseley Instruments */
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/* Niels A. Moseley */
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/* */
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/* Process: none */
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/* */
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/* Date : 25-03-2019 */
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/* Version: 1.0 */
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/* */
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/********************************************/
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library(processdefs) {
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technology (cmos);
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revision : 1.0;
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time_unit : "1ps";
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pulling_resistance_unit : "1kohm";
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voltage_unit : "1V";
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current_unit : "1uA";
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capacitive_load_unit(1,ff);
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default_inout_pin_cap : 7.0;
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default_input_pin_cap : 7.0;
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default_output_pin_cap : 0.0;
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default_fanout_load : 1.0;
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default_wire_load_capacitance : 0.1;
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default_wire_load_resistance : 1.0e-3;
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default_wire_load_area : 0.0;
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nom_process : 1.0;
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nom_temperature : 25.0;
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nom_voltage : 1.2;
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delay_model : generic_cmos;
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define_cell_area(bond_pads,pad_slots)
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input_voltage(cmos) {
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vil : 0.3 * VDD ;
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vih : 0.7 * VDD ;
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vimin : -0.5 ;
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vimax : VDD + 0.5 ;
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}
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}
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@ -0,0 +1,48 @@
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/*
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Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
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fall_constraint (SETUP_HOLD) formatting.
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*/
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library(supergate) {
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technology (cmos);
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revision : 1.0;
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cell (DFF) {
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cell_footprint : dff;
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area : 50;
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pin(D) {
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direction : input;
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capacitance : 0.002;
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timing() {
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related_pin : "CK";
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timing_type : setup_rising;
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fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
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"0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
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"0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
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"0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
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"1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
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}
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}
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pin(CK) {
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direction : input;
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clock : true;
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capacitance : 0.00290;
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}
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ff(IQ,IQN) {
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clocked_on : "CK";
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next_state : "D";
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}
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pin(Q) {
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direction : output;
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capacitance : 0.003;
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max_capacitance : 0.3;
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}
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cell_leakage_power : 0.3;
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}
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}
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