mirror of https://github.com/YosysHQ/yosys.git
abc9_ops: cope with (* abc9_flop *) in place of (* abc9_box_id *)
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48984a7605
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@ -318,7 +318,7 @@ struct XAigerWriter
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc9_box_id"));
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log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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@ -117,7 +117,7 @@ void check(RTLIL::Design *design)
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if (wire->port_output) num_outputs++;
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}
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if (num_outputs != 1)
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log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
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log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
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}
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}
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}
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@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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log_assert(cell);
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RTLIL::Module* box_module = design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
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continue;
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cell->attributes["\\abc9_box_seq"] = box_count++;
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