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aiger: -xaiger to parse initial state back into (* init *) on Q wire
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@ -802,7 +802,8 @@ void AigerReader::post_process()
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ff->setPort(ID::C, r.first->second);
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ff->setPort(ID::C, r.first->second);
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ff->setPort(ID::D, d);
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ff->setPort(ID::D, d);
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ff->setPort(ID::Q, q);
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ff->setPort(ID::Q, q);
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ff->attributes[ID::abc9_init] = initial_state[i];
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log_assert(GetSize(q) == 1);
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q->attributes[ID::init] = initial_state[i];
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}
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}
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dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
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dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
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