mirror of https://github.com/YosysHQ/yosys.git
Added yosys-smtbmc -S
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@ -22,6 +22,7 @@ import os, sys, getopt, re
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from smtio import smtio, smtopts, mkvcd
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skip_steps = 0
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step_size = 1
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num_steps = 20
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vcdfile = None
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tempind = False
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@ -40,6 +41,9 @@ yosys-smtbmc [options] <yosys_smt2_output>
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-u <start_step>
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assume asserts in skipped steps in BMC
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-S <step_size>
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proof <step_size> time steps at once
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-c <vcd_filename>
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write counter-example to this VCD file
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(hint: use 'write_smt2 -wires' for maximum
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@ -55,7 +59,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.optstr + "t:u:c:im:")
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opts, args = getopt.getopt(sys.argv[1:], so.optstr + "t:u:S:c:im:")
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except:
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usage()
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@ -69,6 +73,8 @@ for o, a in opts:
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num_steps = int(a)
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elif o == "-u":
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assume_skipped = int(a)
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elif o == "-S":
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step_size = int(a)
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elif o == "-c":
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vcdfile = a
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elif o == "-i":
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@ -122,6 +128,7 @@ def write_vcd_model(steps):
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if tempind:
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retstatus = False
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skip_counter = step_size
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for step in range(num_steps, -1, -1):
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
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smt.write("(assert (%s_u s%d))" % (topmod, step))
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@ -137,6 +144,12 @@ if tempind:
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print("%s Skipping induction in step %d.." % (smt.timestamp(), step))
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continue
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skip_counter += 1
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if skip_counter < step_size:
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print("%s Skipping induction in step %d.." % (smt.timestamp(), step))
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continue
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skip_counter = 0
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print("%s Trying induction in step %d.." % (smt.timestamp(), step))
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if smt.check_sat() == "sat":
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@ -152,8 +165,9 @@ if tempind:
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else: # not tempind
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step = 0
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retstatus = True
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for step in range(num_steps+1):
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while step < num_steps:
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smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
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smt.write("(assert (%s_u s%d))" % (topmod, step))
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@ -169,23 +183,38 @@ else: # not tempind
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smt.write("(assert (%s_a s%d))" % (topmod, step))
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else:
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print("%s Skipping step %d.." % (smt.timestamp(), step))
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step += 1
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continue
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last_check_step = step
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for i in range(1, step_size):
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if step+i < num_steps:
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smt.write("(declare-fun s%d () %s_s)" % (step+i, topmod))
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smt.write("(assert (%s_u s%d))" % (topmod, step+i))
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smt.write("(assert (%s_t s%d s%d))" % (topmod, step+i-1, step+i))
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last_check_step = step+i
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if last_check_step == step:
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print("%s Checking asserts in step %d.." % (smt.timestamp(), step))
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else:
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print("%s Checking asserts in steps %d to %d.." % (smt.timestamp(), step, last_check_step))
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smt.write("(push 1)")
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smt.write("(assert (not (%s_a s%d)))" % (topmod, step))
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smt.write("(assert (not (and %s)))" % " ".join(["(%s_a s%d)" % (topmod, i) for i in range(step, last_check_step+1)]))
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if smt.check_sat() == "sat":
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print("%s BMC failed!" % smt.timestamp())
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if vcdfile is not None:
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write_vcd_model(step+1)
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write_vcd_model(step+step_size)
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retstatus = False
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break
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else: # unsat
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smt.write("(pop 1)")
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smt.write("(assert (%s_a s%d))" % (topmod, step))
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for i in range(step, last_check_step+1):
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smt.write("(assert (%s_a s%d))" % (topmod, i))
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step += step_size
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smt.write("(exit)")
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