mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
This commit is contained in:
commit
47a1fd3f4a
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@ -756,12 +756,6 @@ void AigerReader::post_process()
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}
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}
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for (uint32_t i = 0; i < flopNum; i++) {
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for (uint32_t i = 0; i < flopNum; i++) {
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log_assert(co_count < outputs.size());
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Wire *wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
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RTLIL::Wire *d = outputs[outputs.size() - flopNum + i];
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log_assert(d);
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log_assert(d);
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log_assert(d->port_output);
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log_assert(d->port_output);
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@ -803,6 +797,7 @@ void AigerReader::post_process()
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wire->port_input = false;
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wire->port_input = false;
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module->connect(wire, existing);
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module->connect(wire, existing);
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}
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}
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log_debug(" -> %s\n", log_id(escaped_s));
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}
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}
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else if (index > 0) {
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else if (index > 0) {
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std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
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std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
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@ -816,8 +811,8 @@ void AigerReader::post_process()
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module->connect(wire, existing);
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module->connect(wire, existing);
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wire->port_input = false;
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wire->port_input = false;
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}
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}
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log_debug(" -> %s\n", log_id(indexed_name));
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}
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}
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log_debug(" -> %s\n", log_id(wire));
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}
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}
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else if (type == "output") {
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else if (type == "output") {
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log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
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log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
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@ -839,6 +834,7 @@ void AigerReader::post_process()
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module->connect(wire, existing);
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module->connect(wire, existing);
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wire = existing;
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wire = existing;
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}
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}
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log_debug(" -> %s\n", log_id(escaped_s));
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}
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}
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else if (index > 0) {
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else if (index > 0) {
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std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
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std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
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@ -852,8 +848,8 @@ void AigerReader::post_process()
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module->connect(wire, existing);
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module->connect(wire, existing);
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wire->port_output = false;
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wire->port_output = false;
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}
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}
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log_debug(" -> %s\n", log_id(indexed_name));
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}
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}
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log_debug(" -> %s\n", log_id(wire));
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int init;
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int init;
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mf >> init;
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mf >> init;
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if (init < 2)
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if (init < 2)
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