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Fix handling of x-bits in EDIF back-end

This commit is contained in:
Clifford Wolf 2017-07-11 17:38:19 +02:00 committed by GitHub
parent 9557fd2a36
commit 479be3cec7
1 changed files with 11 additions and 1 deletions
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12
backends/edif/edif.cc
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@ -374,7 +374,17 @@ struct EdifBackend : public Backend {
} }
for (auto &it : net_join_db) { for (auto &it : net_join_db) {
RTLIL::SigBit sig = it.first; RTLIL::SigBit sig = it.first;
if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) if (sig.wire == NULL && sig != RTLIL::State::S0 && sig != RTLIL::State::S1) {
if (sig == RTLIL::State::Sx) {
for (auto &ref : it.second)
log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str());
sig = RTLIL::State::S0;
} else {
for (auto &ref : it.second)
log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str());
log_abort();
}
}
log_abort(); log_abort();
std::string netname; std::string netname;
if (sig == RTLIL::State::S0) if (sig == RTLIL::State::S0)