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Update CHANGELOG and CODEOWNERS

This commit is contained in:
Miodrag Milanovic 2021-12-01 08:42:37 +01:00
parent 707d98b06c
commit 4792d925fc
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CHANGELOG
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@ -5,6 +5,27 @@ List of major changes and improvements between releases
Yosys 0.11 .. Yosys 0.11-dev Yosys 0.11 .. Yosys 0.11-dev
-------------------------- --------------------------
* Various
- Added iopadmap native support for negative-polarity output enable
- ABC update
* SystemVerilog
- Support parameters using struct as a wiretype
* New commands and options
- Added "-genlib" option to "abc" pass
- Added "sta" very crude static timing analysis pass
* Verific support
- Fixed memory block size in import
* New back-ends
- Added support for GateMate FPGA from Cologne Chip AG
* Intel ALM support
- Added preliminary Arria V support
Yosys 0.10 .. Yosys 0.11 Yosys 0.10 .. Yosys 0.11
-------------------------- --------------------------

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CODEOWNERS
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@ -32,6 +32,7 @@ frontends/ast/ @zachjs
techlibs/intel_alm/ @ZirconiumX techlibs/intel_alm/ @ZirconiumX
techlibs/gowin/ @pepijndevos techlibs/gowin/ @pepijndevos
techlibs/gatemate/ @pu-cc
# pyosys # pyosys
misc/*.py @btut misc/*.py @btut