mirror of https://github.com/YosysHQ/yosys.git
New $mem simlib model
This commit is contained in:
Clifford Wolf
parent
bbf89c4dc6
commit
474831643c
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@ -1518,107 +1518,48 @@ input [WR_PORTS*WIDTH-1:0] WR_EN;
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input [WR_PORTS*ABITS-1:0] WR_ADDR;
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input [WR_PORTS*ABITS-1:0] WR_ADDR;
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input [WR_PORTS*WIDTH-1:0] WR_DATA;
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input [WR_PORTS*WIDTH-1:0] WR_DATA;
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reg [WIDTH-1:0] data [SIZE-1:0];
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reg [WIDTH-1:0] memory [SIZE-1:0];
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reg update_async_rd;
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genvar i;
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integer i, j;
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generate
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reg [WR_PORTS-1:0] LAST_WR_CLK;
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reg [RD_PORTS-1:0] LAST_RD_CLK;
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for (i = 0; i < RD_PORTS; i = i+1) begin:rd
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function port_active;
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if (RD_CLK_ENABLE[i] == 0) begin:rd_noclk
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input clk_enable;
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always @(RD_ADDR or update_async_rd)
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input clk_polarity;
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RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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input last_clk;
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end else
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input this_clk;
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if (RD_TRANSPARENT[i] == 1) begin:rd_transparent
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begin
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reg [ABITS-1:0] addr_buf;
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casez ({clk_enable, clk_polarity, last_clk, this_clk})
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if (RD_CLK_POLARITY[i] == 1) begin:rd_trans_posclk
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4'b0???: port_active = 1;
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always @(posedge RD_CLK[i])
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4'b1101: port_active = 1;
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addr_buf <= RD_ADDR[i*ABITS +: ABITS];
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4'b1010: port_active = 1;
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end else begin:rd_trans_negclk
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default: port_active = 0;
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always @(negedge RD_CLK[i])
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endcase
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addr_buf <= RD_ADDR[i*ABITS +: ABITS];
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end
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end
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endfunction
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always @(addr_buf or update_async_rd)
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RD_DATA[i*WIDTH +: WIDTH] <= data[addr_buf - OFFSET];
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always @* begin
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end else begin:rd_notransparent
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if (RD_CLK_POLARITY[i] == 1) begin:rd_notrans_posclk
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if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
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always @(posedge RD_CLK[i])
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end else begin:rd_notrans_negclk
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always @(negedge RD_CLK[i])
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RD_DATA[i*WIDTH +: WIDTH] <= data[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end
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end
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end
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end
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for (i = 0; i < WR_PORTS; i = i+1) begin:wr
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for (i = 0; i < WR_PORTS; i = i+1) begin
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integer k, n;
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if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
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reg found_collision, run_update;
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for (j = 0; j < WIDTH; j = j+1)
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if (WR_CLK_ENABLE[i] == 0) begin:wr_noclk
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if (WR_EN[i*WIDTH+j])
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always @(WR_ADDR or WR_DATA or WR_EN) begin
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memory[WR_ADDR[i*ABITS +: ABITS] - OFFSET][j] = WR_DATA[i*WIDTH+j];
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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end
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if (run_update) begin
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update_async_rd <= 1;
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update_async_rd <= 0;
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end
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end
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end else
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if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
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always @(posedge WR_CLK[i]) begin
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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end
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if (run_update) begin
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update_async_rd <= 1;
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update_async_rd <= 0;
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end
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end
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end else begin:rd_negclk
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always @(negedge WR_CLK[i]) begin
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run_update = 0;
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for (n = 0; n < WIDTH; n = n+1) begin
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if (WR_EN[i*WIDTH + n]) begin
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found_collision = 0;
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for (k = i+1; k < WR_PORTS; k = k+1)
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if (WR_EN[k*WIDTH + n] && WR_ADDR[i*ABITS +: ABITS] == WR_ADDR[k*ABITS +: ABITS])
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found_collision = 1;
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if (!found_collision) begin
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data[WR_ADDR[i*ABITS +: ABITS] - OFFSET][n] <= WR_DATA[i*WIDTH + n];
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run_update = 1;
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end
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end
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end
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if (run_update) begin
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update_async_rd <= 1;
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update_async_rd <= 0;
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end
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end
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end
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end
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end
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endgenerate
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for (i = 0; i < RD_PORTS; i = i+1) begin
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if ((RD_TRANSPARENT[i] || !RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]))
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RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
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end
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LAST_RD_CLK <= RD_CLK;
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LAST_WR_CLK <= WR_CLK;
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end
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endmodule
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endmodule
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