mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1708 from rqou/coolrunner2-buf-fix
coolrunner2: Separate and improve buffer cell insertion pass
This commit is contained in:
Claire Wolf
GitHub
commit
47228feb77
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@ -1,6 +1,7 @@
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OBJS += techlibs/coolrunner2/synth_coolrunner2.o
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OBJS += techlibs/coolrunner2/synth_coolrunner2.o
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OBJS += techlibs/coolrunner2/coolrunner2_sop.o
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OBJS += techlibs/coolrunner2/coolrunner2_sop.o
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OBJS += techlibs/coolrunner2/coolrunner2_fixup.o
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_latch.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
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$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
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@ -0,0 +1,161 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 R. Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Coolrunner2FixupPass : public Pass {
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Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" coolrunner2_fixup [options] [selection]\n");
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log("\n");
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log("Insert necessary buffer cells for CoolRunner-II architecture.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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// Find all the FF outputs
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pool<SigBit> sig_fed_by_ff;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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auto output = sigmap(cell->getPort("\\Q")[0]);
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sig_fed_by_ff.insert(output);
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}
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}
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// Find all the XOR outputs
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pool<SigBit> sig_fed_by_xor;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\MACROCELL_XOR")
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{
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auto output = sigmap(cell->getPort("\\OUT")[0]);
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sig_fed_by_xor.insert(output);
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}
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}
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// Find all the input/inout outputs
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pool<SigBit> sig_fed_by_io;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\IBUF", "\\IOBUFE"))
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{
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if (cell->hasPort("\\O")) {
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auto output = sigmap(cell->getPort("\\O")[0]);
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sig_fed_by_io.insert(output);
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}
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}
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}
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// Start by buffering FF inputs. FF inputs can only come from either
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// an IO pin or from an XOR. Otherwise AND/XOR cells need to be inserted.
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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SigBit input;
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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input = sigmap(cell->getPort("\\T")[0]);
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else
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input = sigmap(cell->getPort("\\D")[0]);
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if (!sig_fed_by_xor[input] && !sig_fed_by_io[input])
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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auto and_to_xor_wire = module->addWire(NEW_ID);
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auto xor_to_ff_wire = module->addWire(NEW_ID);
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auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", 1);
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and_cell->setParam("\\COMP_INP", 0);
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and_cell->setPort("\\OUT", and_to_xor_wire);
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and_cell->setPort("\\IN", input);
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and_cell->setPort("\\IN_B", SigSpec());
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auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
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xor_cell->setPort("\\OUT", xor_to_ff_wire);
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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cell->setPort("\\T", xor_to_ff_wire);
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else
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cell->setPort("\\D", xor_to_ff_wire);
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}
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}
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}
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// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\IOBUFE")
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{
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SigBit input = sigmap(cell->getPort("\\I")[0]);
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// Special case: constant 0 and 1 are handled by xc2par
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if (input == SigBit(true) || input == SigBit(false)) {
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log("Not buffering constant IO to \"%s\"\n", cell->name.c_str());
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continue;
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}
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if (!sig_fed_by_xor[input] && !sig_fed_by_ff[input])
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{
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log("Buffering input to \"%s\"\n", cell->name.c_str());
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auto and_to_xor_wire = module->addWire(NEW_ID);
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auto xor_to_io_wire = module->addWire(NEW_ID);
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auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", 1);
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and_cell->setParam("\\COMP_INP", 0);
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and_cell->setPort("\\OUT", and_to_xor_wire);
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and_cell->setPort("\\IN", input);
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and_cell->setPort("\\IN_B", SigSpec());
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auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
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xor_cell->setPort("\\OUT", xor_to_io_wire);
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cell->setPort("\\I", xor_to_io_wire);
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}
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}
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}
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}
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}
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} Coolrunner2FixupPass;
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PRIVATE_NAMESPACE_END
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@ -248,60 +248,6 @@ struct Coolrunner2SopPass : public Pass {
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}
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}
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}
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}
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// In some cases we can get a FF feeding straight into an FF. This is not possible, so we need to insert
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// some AND/XOR cells in the middle to make it actually work.
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// Find all the FF outputs
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pool<SigBit> sig_fed_by_ff;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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auto output = sigmap(cell->getPort("\\Q")[0]);
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sig_fed_by_ff.insert(output);
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}
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}
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// Look at all the FF inputs
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
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"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
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{
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SigBit input;
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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input = sigmap(cell->getPort("\\T")[0]);
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else
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input = sigmap(cell->getPort("\\D")[0]);
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if (sig_fed_by_ff[input])
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{
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printf("Buffering input to \"%s\"\n", cell->name.c_str());
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auto and_to_xor_wire = module->addWire(NEW_ID);
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auto xor_to_ff_wire = module->addWire(NEW_ID);
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auto and_cell = module->addCell(NEW_ID, "\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", 1);
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and_cell->setParam("\\COMP_INP", 0);
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and_cell->setPort("\\OUT", and_to_xor_wire);
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and_cell->setPort("\\IN", input);
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and_cell->setPort("\\IN_B", SigSpec());
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auto xor_cell = module->addCell(NEW_ID, "\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", false);
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xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
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xor_cell->setPort("\\OUT", xor_to_ff_wire);
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if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
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cell->setPort("\\T", xor_to_ff_wire);
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else
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cell->setPort("\\D", xor_to_ff_wire);
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}
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}
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}
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// Actually do the removal now that we aren't iterating
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// Actually do the removal now that we aren't iterating
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for (auto cell : cells_to_remove)
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for (auto cell : cells_to_remove)
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{
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{
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@ -178,6 +178,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
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run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
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run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
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run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
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run("attrmvcp -attr src -attr LOC t:IOBUFE n:*");
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run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");
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run("attrmvcp -attr src -attr LOC -driven t:IBUF n:*");
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run("coolrunner2_fixup");
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run("splitnets");
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run("splitnets");
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run("clean");
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run("clean");
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}
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}
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