mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1183 from whitequark/ice40-always-relut
synth_ice40: switch -relut to be always on
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commit
463f710066
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@ -67,9 +67,6 @@ struct SynthIce40Pass : public ScriptPass
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -relut\n");
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log(" combine LUTs after synthesis\n");
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log("\n");
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log(" -nocarry\n");
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log(" do not use SB_CARRY cells in output netlist\n");
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log("\n");
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@ -78,7 +75,7 @@ struct SynthIce40Pass : public ScriptPass
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log("\n");
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log(" -dffe_min_ce_use <min_ce_use>\n");
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log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
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log(" than min_ce_use SB_DFFE*in output netlist\n");
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log(" than min_ce_use SB_DFFE* in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use SB_RAM40_4K* cells in output netlist\n");
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@ -106,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
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}
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string top_opt, blif_file, edif_file, json_file, abc, device_opt;
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bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
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bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
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int min_ce_use;
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void clear_flags() YS_OVERRIDE
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@ -122,7 +119,6 @@ struct SynthIce40Pass : public ScriptPass
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dsp = false;
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flatten = true;
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retime = false;
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relut = false;
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noabc = false;
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abc2 = false;
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vpr = false;
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@ -175,7 +171,7 @@ struct SynthIce40Pass : public ScriptPass
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continue;
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}
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if (args[argidx] == "-relut") {
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relut = true;
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// removed, opt_lut is always run
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continue;
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}
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if (args[argidx] == "-nocarry") {
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@ -347,10 +343,8 @@ struct SynthIce40Pass : public ScriptPass
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run(abc + " -dress -lut 4", "(skip if -noabc)");
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}
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run("clean");
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if (relut || help_mode) {
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run("ice40_unlut", " (only if -relut)");
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run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
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}
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run("ice40_unlut");
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run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
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}
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if (check_label("map_cells"))
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