riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Be more conservative with merging large cells into FSMs

This commit is contained in:
Clifford Wolf 2017-01-26 09:19:28 +01:00
parent 49b8160488
commit 45e10c1c89
1 changed files with 17 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
passes/fsm/fsm_expand.cc
View File

@ -54,13 +54,27 @@ struct FsmExpand
if (cell->getPort("\\A").size() < 2) if (cell->getPort("\\A").size() < 2)
return true; return true;
int in_bits = 0;
RTLIL::SigSpec new_signals; RTLIL::SigSpec new_signals;
if (cell->hasPort("\\A"))
if (cell->hasPort("\\A")) {
in_bits += GetSize(cell->getPort("\\A"));
new_signals.append(assign_map(cell->getPort("\\A"))); new_signals.append(assign_map(cell->getPort("\\A")));
if (cell->hasPort("\\B")) }
if (cell->hasPort("\\B")) {
in_bits += GetSize(cell->getPort("\\B"));
new_signals.append(assign_map(cell->getPort("\\B"))); new_signals.append(assign_map(cell->getPort("\\B")));
if (cell->hasPort("\\S")) }
if (cell->hasPort("\\S")) {
in_bits += GetSize(cell->getPort("\\S"));
new_signals.append(assign_map(cell->getPort("\\S"))); new_signals.append(assign_map(cell->getPort("\\S")));
}
if (in_bits > 8)
return false;
if (cell->hasPort("\\Y")) if (cell->hasPort("\\Y"))
new_signals.append(assign_map(cell->getPort("\\Y"))); new_signals.append(assign_map(cell->getPort("\\Y")));