riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 

abc9: fixes around handling combinatorial loops
This commit is contained in:
Eddie Hung 2020-06-03 17:35:46 -07:00 committed by GitHub
parent 46ed0db2ec 8a11019d38
commit 45cd323055
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 18 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger/xaiger.cc
View File

@ -156,7 +156,7 @@ struct XAigerWriter
// promote keep wires // promote keep wires
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->get_bool_attribute(ID::keep)) if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep))
sigmap.add(wire); sigmap.add(wire);
for (auto wire : module->wires()) { for (auto wire : module->wires()) {

6
passes/techmap/abc9_ops.cc
View File

@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
bit_users[bit].insert(cell->name); bit_users[bit].insert(cell->name);
if (cell->output(conn.first) && !abc9_flop) if (cell->output(conn.first) && !abc9_flop)
for (auto bit : sigmap(conn.second)) for (const auto &chunk : conn.second.chunks())
bit_drivers[bit].insert(cell->name); if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
for (auto b : sigmap(SigSpec(chunk)))
bit_drivers[b].insert(cell->name);
} }
toposort.node(cell->name); toposort.node(cell->name);
} }

13
tests/arch/ecp5/latches_abc9.ys Normal file
View File

@ -0,0 +1,13 @@
read_verilog <<EOT
module top(input e, d, output q);
reg l;
always @*
if (e)
l = ~d;
assign q = ~l;
endmodule
EOT
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9
select -assert-count 2 t:LUT4
select -assert-none t:LUT4 %% t:* %D