diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index 502e21022..866efae77 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -31,7 +31,7 @@ struct MemoryPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" memory [-nomap] [selection]\n"); + log(" memory [-nomap] [-bram ] [selection]\n"); log("\n"); log("This pass calls all the other memory_* passes in a useful order:\n"); log("\n"); @@ -40,7 +40,8 @@ struct MemoryPass : public Pass { log(" memory_share\n"); log(" opt_clean\n"); log(" memory_collect\n"); - log(" memory_map (skipped if called with -nomap)\n"); + log(" memory_bram -rules (when called with -bram)\n"); + log(" memory_map (skipped if called with -nomap)\n"); log("\n"); log("This converts memories to word-wide DFFs and address decoders\n"); log("or multiport memory blocks if called with the -nomap option.\n"); @@ -49,6 +50,7 @@ struct MemoryPass : public Pass { virtual void execute(std::vector args, RTLIL::Design *design) { bool flag_nomap = false; + string memory_bram_opts; log_header("Executing MEMORY pass.\n"); log_push(); @@ -59,6 +61,10 @@ struct MemoryPass : public Pass { flag_nomap = true; continue; } + if (argidx+1 < args.size() && args[argidx] == "-bram") { + memory_bram_opts += " -rules " + args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -69,6 +75,9 @@ struct MemoryPass : public Pass { Pass::call(design, "opt_clean"); Pass::call(design, "memory_collect"); + if (!memory_bram_opts.empty()) + Pass::call(design, "memory_bram" + memory_bram_opts); + if (!flag_nomap) Pass::call(design, "memory_map"); diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index cb8295d1b..19a235c7a 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v