mirror of https://github.com/YosysHQ/yosys.git
machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.
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@ -0,0 +1,8 @@
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read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 10 t:LUT4
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:FACADE_FF
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select -assert-none t:FACADE_FF %% t:* %D
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select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
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design -load read
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hierarchy -top dffe
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@ -16,4 +16,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 2 t:FACADE_FF t:LUT4
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select -assert-none t:FACADE_FF t:LUT4 %% t:* %D
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select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D
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@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 9 t:LUT4
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select -assert-none t:LUT4 %% t:* %D
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select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
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