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Improvements in equiv_struct

This commit is contained in:
Clifford Wolf 2015-10-24 23:04:17 +02:00
parent 7f110e7018
commit 453736d918
1 changed files with 22 additions and 1 deletions
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23
passes/equiv/equiv_struct.cc
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@ -116,9 +116,15 @@ struct EquivStructWorker
{ {
log(" Starting new iteration.\n"); log(" Starting new iteration.\n");
pool<SigBit> equiv_inputs;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv") { if (cell->type == "$equiv") {
equiv_bits.add(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\B"))); SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
cells_by_type[cell->type].insert(cell->name); cells_by_type[cell->type].insert(cell->name);
} else } else
if (module->design->selected(module, cell)) { if (module->design->selected(module, cell)) {
@ -126,6 +132,21 @@ struct EquivStructWorker
cells_by_type[cell->type].insert(cell->name); cells_by_type[cell->type].insert(cell->name);
} }
for (auto cell_name : cells_by_type["$equiv"]) {
Cell *cell = module->cell(cell_name);
SigBit sig_a = sigmap(cell->getPort("\\A").as_bit());
SigBit sig_b = sigmap(cell->getPort("\\B").as_bit());
SigBit sig_y = sigmap(cell->getPort("\\Y").as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", log_id(cell));
module->remove(cell);
merge_count++;
}
}
if (merge_count > 0)
return;
for (auto &it : cells_by_type) for (auto &it : cells_by_type)
{ {
if (it.second.size() <= 1) if (it.second.size() <= 1)