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synth_xilinx: Support latches, remove used-up FF init values. 

Fixes #1387.
This commit is contained in:
Marcin Kościelnicki 2019-09-23 12:41:42 +02:00 committed by Marcin Kościelnicki
parent d5f0794a53
commit 4535f2c694
3 changed files with 77 additions and 2 deletions
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1
CHANGELOG
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@ -49,6 +49,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
Yosys 0.8 .. Yosys 0.9
----------------------

38
techlibs/xilinx/xc6s_ff_map.v
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@ -18,7 +18,12 @@
*/
// ============================================================================
// FF mapping
// FF mapping for Spartan 6. The primitives used are the same as Series 7,
// but with one major difference: the initial value is implied by the
// primitive type used (FFs with reset pin must have INIT set to 0 or x, FFs
// with set pin must have INIT set to 1 or x). For Yosys primitives without
// set/reset, this means we have to pick the primitive type based on the INIT
// value.
`ifndef _NO_FFS
@ -29,6 +34,7 @@ module \$_DFF_N_ (input D, C, output Q);
else
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_P_ (input D, C, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -37,6 +43,7 @@ module \$_DFF_P_ (input D, C, output Q);
else
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_NP_ (input D, C, E, output Q);
@ -46,6 +53,7 @@ module \$_DFFE_NP_ (input D, C, E, output Q);
else
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP_ (input D, C, E, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -54,6 +62,7 @@ module \$_DFFE_PP_ (input D, C, E, output Q);
else
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NN0_ (input D, C, R, output Q);
@ -63,6 +72,7 @@ module \$_DFF_NN0_ (input D, C, R, output Q);
else
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -71,6 +81,7 @@ module \$_DFF_NP0_ (input D, C, R, output Q);
else
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -79,6 +90,7 @@ module \$_DFF_PN0_ (input D, C, R, output Q);
else
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -87,6 +99,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
else
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NN1_ (input D, C, R, output Q);
@ -96,6 +109,7 @@ module \$_DFF_NN1_ (input D, C, R, output Q);
else
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -104,6 +118,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q);
else
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PN1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -112,6 +127,7 @@ module \$_DFF_PN1_ (input D, C, R, output Q);
else
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
@ -120,6 +136,26 @@ module \$_DFF_PP1_ (input D, C, R, output Q);
else
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_N_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
else
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_P_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
LDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .PRE(1'b0));
else
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
`endif

40
techlibs/xilinx/xc7_ff_map.v
View File

@ -18,60 +18,98 @@
*/
// ============================================================================
// FF mapping
// FF mapping for Virtex 6, Series 7 and Ultrascale. These families support
// the following features:
//
// - a CLB flip-flop can be used as a latch or as a flip-flop
// - a CLB flip-flop has the following pins:
//
// - data input
// - clock (or gate for latches) (with optional inversion)
// - clock enable (or gate enable, which is just ANDed with gate — unused by
// synthesis)
// - either a set or a reset input, which (for FFs) can be either
// synchronous or asynchronous (with optional inversion)
// - data output
//
// - a flip-flop also has an initial value, which is set at device
// initialization (or whenever GSR is asserted)
`ifndef _NO_FFS
module \$_DFF_N_ (input D, C, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_P_ (input D, C, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_NP_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFFE_PP_ (input D, C, E, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NN0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PN0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NN1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_NP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PN1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DFF_PP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_N_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$_DLATCH_P_ (input E, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
LDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1'b1), .CLR(1'b0));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
`endif