Add to CHANGELOG

This commit is contained in:
Eddie Hung 2019-11-22 15:35:08 -08:00
parent 856a3dc98d
commit 450ad0e9ba
1 changed files with 1 additions and 0 deletions

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@ -53,6 +53,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
- Added "clkpart" pass
Yosys 0.8 .. Yosys 0.9
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