mirror of https://github.com/YosysHQ/yosys.git
Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
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@ -55,14 +55,13 @@ module \$shiftx (A, B, Y);
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if (B_SIGNED) begin
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if (B_WIDTH < 4 || A_WIDTH <= 4)
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wire _TECHMAP_FAIL_ = 1;
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else
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// Since negative indices are out of the range of A
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// and hence return 'bx, drop the sign bit
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else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
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// Optimisation to remove B_SIGNED if sign bit of B is constant-0
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\$__XILINX_SHIFTX #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(0),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH($clog2(A_WIDTH*B_WIDTH)),
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.B_WIDTH(B_WIDTH-1'd1),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
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