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Merge pull request #3560 from YosysHQ/verific_conf 

Support importing verilog configurations using Verific
This commit is contained in:
Miodrag Milanović 2022-11-25 17:40:57 +01:00 committed by GitHub
parent c55c514cdb f764cd1655
commit 448a796e15
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 43 additions and 8 deletions
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47
frontends/verific/verific.cc
View File

@ -47,6 +47,7 @@ USING_YOSYS_NAMESPACE
#include "VeriModule.h" #include "VeriModule.h"
#include "VeriWrite.h" #include "VeriWrite.h"
#include "VeriLibrary.h" #include "VeriLibrary.h"
#include "VeriExpression.h"
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
#include "vhdl_file.h" #include "vhdl_file.h"
@ -2267,7 +2268,7 @@ struct VerificExtNets
} }
}; };
void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top) std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
{ {
verific_sva_fsm_limit = 16; verific_sva_fsm_limit = 16;
@ -2300,6 +2301,18 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
if (veri_module) { if (veri_module) {
veri_modules.InsertLast(veri_module); veri_modules.InsertLast(veri_module);
if (veri_module->IsConfiguration()) {
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
top = veri_module->GetName();
}
} }
// Also elaborate all root modules since they may contain bind statements // Also elaborate all root modules since they may contain bind statements
@ -2378,6 +2391,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
if (!verific_error_msg.empty()) if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str()); log_error("%s\n", verific_error_msg.c_str());
return top;
} }
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END
@ -2527,10 +2541,10 @@ struct VerificPass : public Pass {
log("is printed, such as VERI-1209.\n"); log("is printed, such as VERI-1209.\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -import [options] <top-module>..\n"); log(" verific -import [options] <top>..\n");
log("\n"); log("\n");
log("Elaborate the design for the specified top modules, import to Yosys and\n"); log("Elaborate the design for the specified top modules or configurations, import to\n");
log("reset the internal state of Verific.\n"); log("Yosys and reset the internal state of Verific.\n");
log("\n"); log("\n");
log("Import options:\n"); log("Import options:\n");
log("\n"); log("\n");
@ -3246,8 +3260,29 @@ struct VerificPass : public Pass {
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
if (veri_module) { if (veri_module) {
log("Adding Verilog module '%s' to elaboration queue.\n", name); if (veri_module->IsConfiguration()) {
veri_modules.InsertLast(veri_module); log("Adding Verilog configuration '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);
top_mod_names.erase(name);
VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
VeriName *module_name;
int i;
FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
VeriLibrary *lib = veri_module->GetLibrary() ;
if (module_name && module_name->IsHierName()) {
VeriName *prefix = module_name->GetPrefix() ;
const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
}
veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
top_mod_names.insert(veri_module->GetName());
}
} else {
log("Adding Verilog module '%s' to elaboration queue.\n", name);
veri_modules.InsertLast(veri_module);
}
continue; continue;
} }
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT

2
frontends/verific/verific.h
View File

@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
extern int verific_verbose; extern int verific_verbose;
extern bool verific_import_pending; extern bool verific_import_pending;
extern void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string()); extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
extern pool<int> verific_sva_prims; extern pool<int> verific_sva_prims;

2
passes/hierarchy/hierarchy.cc
View File

@ -960,7 +960,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) { if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) { if (verific_import_pending) {
verific_import(design, parameters, load_top_mod); load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod)); top_mod = design->module(RTLIL::escape_id(load_top_mod));
} }
#endif #endif