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Fixed a gcc compiler warning [-Wparentheses]

This commit is contained in:
Clifford Wolf 2013-03-03 22:45:06 +01:00
parent bc8d94b4ae
commit 441e5fbfca
1 changed files with 2 additions and 1 deletions
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3
backends/verilog/verilog_backend.cc
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@ -139,12 +139,13 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
if (reg_wires.count(sig.chunks[0].wire->name) == 0) if (reg_wires.count(sig.chunks[0].wire->name) == 0)
return false; return false;
reg_name = id(sig.chunks[0].wire->name); reg_name = id(sig.chunks[0].wire->name);
if (sig.width != sig.chunks[0].wire->width) if (sig.width != sig.chunks[0].wire->width) {
if (sig.width == 1) if (sig.width == 1)
reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset); reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset);
else else
reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset + sig.chunks[0].width - 1, reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset + sig.chunks[0].width - 1,
sig.chunks[0].wire->start_offset + sig.chunks[0].offset); sig.chunks[0].wire->start_offset + sig.chunks[0].offset);
}
return true; return true;
} }