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This commit is contained in:
Eddie Hung 2019-09-20 14:24:31 -07:00
parent 53817b8575
commit 4401e5f142
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techlibs/xilinx/abc_model.v
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@ -47,7 +47,7 @@ endmodule
// Modules used to model the comb/seq behaviour of DSP48E1 // Modules used to model the comb/seq behaviour of DSP48E1
// With abc_map.v responsible for splicing the below modules // With abc_map.v responsible for splicing the below modules
// into between the combinatorial DSP48E1 box (e.g. disconnecting // between the combinatorial DSP48E1 box (e.g. disconnecting
// A when AREG, MREG or PREG is enabled and splicing in the // A when AREG, MREG or PREG is enabled and splicing in the
// "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below) // "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
// this acts to first disables the combinatorial path (as there // this acts to first disables the combinatorial path (as there