diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index d4e035051..3edf6c8fc 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -867,8 +867,12 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
 	parameter INIT = 0;
 endmodule
 
+(* blackbox, keep *)
 module GSR (input GSRI);
-	wire GSRO = GSRI;
+endmodule
+
+(* blackbox, keep *)
+module BANDGAP (input BGEN);
 endmodule
 
 (* abc9_box, lib_whitebox *)
diff --git a/techlibs/gowin/cells_xtra.py b/techlibs/gowin/cells_xtra.py
index 4d117e428..224ece02f 100644
--- a/techlibs/gowin/cells_xtra.py
+++ b/techlibs/gowin/cells_xtra.py
@@ -13,7 +13,7 @@ class State(Enum):
     IN_MODULE = auto()
     IN_PARAMETER = auto()
 
-_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
+_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
           'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
           'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
           'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',
diff --git a/techlibs/gowin/cells_xtra.v b/techlibs/gowin/cells_xtra.v
index cf914f38e..6ab50a097 100644
--- a/techlibs/gowin/cells_xtra.v
+++ b/techlibs/gowin/cells_xtra.v
@@ -1681,10 +1681,6 @@ endmodule
 module ADC (...);
 endmodule
 
-module BANDGAP (...);
-input BGEN;
-endmodule
-
 module CLKDIV2 (...);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;