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Addressed review comments

This commit is contained in:
Miodrag Milanovic 2019-12-21 20:23:23 +01:00
parent 1937091f62
commit 436fea9e69
2 changed files with 3 additions and 3 deletions
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5
techlibs/xilinx/synth_xilinx.cc
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@ -85,7 +85,8 @@ struct SynthXilinxPass : public ScriptPass
log(" do not use DSP48E1s to implement multipliers and associated logic\n"); log(" do not use DSP48E1s to implement multipliers and associated logic\n");
log("\n"); log("\n");
log(" -noiopad\n"); log(" -noiopad\n");
log(" disable I/O buffer insertion\n"); log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows)\n");
log("\n"); log("\n");
log(" -noclkbuf\n"); log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion\n"); log(" disable automatic clock buffer insertion\n");
@ -210,7 +211,7 @@ struct SynthXilinxPass : public ScriptPass
} }
if (args[argidx] == "-iopad") { if (args[argidx] == "-iopad") {
continue; continue;
} }
if (args[argidx] == "-noiopad") { if (args[argidx] == "-noiopad") {
noiopad = true; noiopad = true;
continue; continue;

1
tests/arch/xilinx/tribuf.ys
View File

@ -7,7 +7,6 @@ synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristate # Constrain all select calls below inside the top module cd tristate # Constrain all select calls below inside the top module
# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
select -assert-count 2 t:IBUF select -assert-count 2 t:IBUF
select -assert-count 1 t:INV select -assert-count 1 t:INV
select -assert-count 1 t:OBUFT select -assert-count 1 t:OBUFT