mirror of https://github.com/YosysHQ/yosys.git
ql_dsp_macc: whitespace. NFC
This commit is contained in:
Emil J. Tywoniak
Martin Povišer
parent
c1d2107fe0
commit
434334ba63
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@ -29,187 +29,186 @@ PRIVATE_NAMESPACE_BEGIN
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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static void create_ql_macc_dsp(ql_dsp_macc_pm &pm, int dsp_version)
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{
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{
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auto &st = pm.st_ql_dsp_macc;
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auto &st = pm.st_ql_dsp_macc;
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log_assert(dsp_version < 3);
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log_assert(dsp_version < 3);
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log_assert(dsp_version > 0);
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log_assert(dsp_version > 0);
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// Get port widths
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// Get port widths
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size_t a_width = GetSize(st.mul->getPort(ID(A)));
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size_t a_width = GetSize(st.mul->getPort(ID(A)));
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size_t b_width = GetSize(st.mul->getPort(ID(B)));
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size_t b_width = GetSize(st.mul->getPort(ID(B)));
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size_t z_width = GetSize(st.ff->getPort(ID(Q)));
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size_t z_width = GetSize(st.ff->getPort(ID(Q)));
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size_t min_width = std::min(a_width, b_width);
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size_t min_width = std::min(a_width, b_width);
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size_t max_width = std::max(a_width, b_width);
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size_t max_width = std::max(a_width, b_width);
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// Signed / unsigned
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// Signed / unsigned
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bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool();
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bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool();
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log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool());
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log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool());
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// Determine DSP type or discard if too narrow / wide
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// Determine DSP type or discard if too narrow / wide
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RTLIL::IdString type;
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RTLIL::IdString type;
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size_t tgt_a_width;
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size_t tgt_a_width;
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size_t tgt_b_width;
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size_t tgt_b_width;
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size_t tgt_z_width;
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size_t tgt_z_width;
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string cell_base_name;
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string cell_base_name;
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string cell_size_name = "";
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string cell_size_name = "";
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string cell_cfg_name = "";
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string cell_cfg_name = "";
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string cell_full_name = "";
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string cell_full_name = "";
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if (dsp_version == 1)
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if (dsp_version == 1)
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cell_base_name = "dsp_t1";
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cell_base_name = "dsp_t1";
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if (dsp_version == 2)
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if (dsp_version == 2)
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cell_base_name = "dspv2";
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cell_base_name = "dspv2";
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if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
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if (min_width <= 2 && max_width <= 2 && z_width <= 4) {
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log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width);
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log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width);
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return;
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return;
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}
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}
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bool reject = false;
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bool reject = false;
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if (dsp_version == 1) {
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if (dsp_version == 1) {
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if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
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if (min_width <= 9 && max_width <= 10 && z_width <= 19) {
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cell_size_name = "_10x9x32";
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cell_size_name = "_10x9x32";
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tgt_a_width = 10;
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tgt_a_width = 10;
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tgt_b_width = 9;
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tgt_b_width = 9;
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tgt_z_width = 19;
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tgt_z_width = 19;
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} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
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} else if (min_width <= 18 && max_width <= 20 && z_width <= 38) {
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cell_size_name = "_20x18x64";
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cell_size_name = "_20x18x64";
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tgt_a_width = 20;
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_b_width = 18;
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tgt_z_width = 38;
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tgt_z_width = 38;
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} else {
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} else {
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reject = true;
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reject = true;
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}
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}
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} else if (dsp_version == 2) {
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} else if (dsp_version == 2) {
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if (min_width <= 9 && max_width <= 16 && z_width <= 25) {
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if (min_width <= 9 && max_width <= 16 && z_width <= 25) {
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cell_size_name = "_16x9x32";
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cell_size_name = "_16x9x32";
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tgt_a_width = 16;
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tgt_a_width = 16;
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tgt_b_width = 9;
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tgt_b_width = 9;
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tgt_z_width = 25;
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tgt_z_width = 25;
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} else if (min_width <= 18 && max_width <= 32 && z_width <= 50) {
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} else if (min_width <= 18 && max_width <= 32 && z_width <= 50) {
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cell_size_name = "_32x18x64";
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cell_size_name = "_32x18x64";
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tgt_a_width = 20;
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tgt_a_width = 20;
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tgt_b_width = 18;
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tgt_b_width = 18;
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tgt_z_width = 50;
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tgt_z_width = 50;
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} else {
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} else {
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reject = true;
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reject = true;
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}
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}
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} else {
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} else {
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log_assert(false);
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log_assert(false);
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}
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}
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if (reject) {
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if (reject) {
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log_debug("\trejected: too wide (%zd %zd %zd) for v%d\n",
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log_debug("\trejected: too wide (%zd %zd %zd) for v%d\n", min_width, max_width, z_width, dsp_version);
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min_width, max_width, z_width, dsp_version);
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return;
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return;
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}
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}
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type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
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type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports");
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log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type));
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log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type));
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for (auto cell : {st.mul, st.add, st.mux, st.ff})
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for (auto cell : {st.mul, st.add, st.mux, st.ff})
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if (cell)
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if (cell)
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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// Add the DSP cell
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// Add the DSP cell
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RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
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RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type);
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// Set attributes
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// Set attributes
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cell->set_bool_attribute(ID(is_inferred), true);
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cell->set_bool_attribute(ID(is_inferred), true);
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// Get input/output data signals
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// Get input/output data signals
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RTLIL::SigSpec sig_a, sig_b, sig_z;
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RTLIL::SigSpec sig_a, sig_b, sig_z;
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sig_a = st.mul->getPort(ID(A));
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sig_a = st.mul->getPort(ID(A));
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sig_b = st.mul->getPort(ID(B));
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sig_b = st.mul->getPort(ID(B));
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sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
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sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D));
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if (a_width < b_width)
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if (a_width < b_width)
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std::swap(sig_a, sig_b);
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std::swap(sig_a, sig_b);
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// Connect input data ports, sign extend / pad with zeros
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// Connect input data ports, sign extend / pad with zeros
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sig_a.extend_u0(tgt_a_width, ab_signed);
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sig_a.extend_u0(tgt_a_width, ab_signed);
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sig_b.extend_u0(tgt_b_width, ab_signed);
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sig_b.extend_u0(tgt_b_width, ab_signed);
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cell->setPort(ID(a_i), sig_a);
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cell->setPort(ID(a_i), sig_a);
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cell->setPort(ID(b_i), sig_b);
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cell->setPort(ID(b_i), sig_b);
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// Connect output data port, pad if needed
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// Connect output data port, pad if needed
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if ((size_t) GetSize(sig_z) < tgt_z_width) {
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if ((size_t)GetSize(sig_z) < tgt_z_width) {
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auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
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auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z));
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sig_z.append(wire);
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sig_z.append(wire);
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}
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}
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cell->setPort(ID(z_o), sig_z);
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cell->setPort(ID(z_o), sig_z);
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// Connect clock, reset and enable
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// Connect clock, reset and enable
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cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK)));
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cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK)));
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RTLIL::SigSpec rst;
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RTLIL::SigSpec rst;
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RTLIL::SigSpec ena;
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RTLIL::SigSpec ena;
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if (st.ff->hasPort(ID(ARST))) {
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if (st.ff->hasPort(ID(ARST))) {
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if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
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if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
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rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
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rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST)));
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} else {
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} else {
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rst = st.ff->getPort(ID(ARST));
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rst = st.ff->getPort(ID(ARST));
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}
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}
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} else {
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} else {
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rst = RTLIL::SigSpec(RTLIL::S0);
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rst = RTLIL::SigSpec(RTLIL::S0);
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}
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}
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if (st.ff->hasPort(ID(EN))) {
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if (st.ff->hasPort(ID(EN))) {
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if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
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if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
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ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
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ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN)));
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} else {
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} else {
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ena = st.ff->getPort(ID(EN));
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ena = st.ff->getPort(ID(EN));
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}
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}
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} else {
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} else {
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ena = RTLIL::SigSpec(RTLIL::S1);
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ena = RTLIL::SigSpec(RTLIL::S1);
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}
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}
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cell->setPort(ID(reset_i), rst);
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cell->setPort(ID(reset_i), rst);
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cell->setPort(ID(load_acc_i), ena);
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cell->setPort(ID(load_acc_i), ena);
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// Insert feedback_i control logic used for clearing / loading the accumulator
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// Insert feedback_i control logic used for clearing / loading the accumulator
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if (st.mux_in_pattern) {
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if (st.mux_in_pattern) {
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RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
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RTLIL::SigSpec sig_s = st.mux->getPort(ID(S));
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// Depending on the mux port ordering insert inverter if needed
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// Depending on the mux port ordering insert inverter if needed
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log_assert(st.mux_ab.in(ID(A), ID(B)));
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log_assert(st.mux_ab.in(ID(A), ID(B)));
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if (st.mux_ab == ID(A))
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if (st.mux_ab == ID(A))
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sig_s = pm.module->Not(NEW_ID, sig_s);
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sig_s = pm.module->Not(NEW_ID, sig_s);
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// Assemble the full control signal for the feedback_i port
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// Assemble the full control signal for the feedback_i port
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RTLIL::SigSpec sig_f;
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RTLIL::SigSpec sig_f;
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sig_f.append(sig_s);
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sig_f.append(sig_s);
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sig_f.append(RTLIL::S0);
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sig_f.append(RTLIL::S0);
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sig_f.append(RTLIL::S0);
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sig_f.append(RTLIL::S0);
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cell->setPort(ID(feedback_i), sig_f);
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cell->setPort(ID(feedback_i), sig_f);
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}
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}
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// No acc clear/load
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// No acc clear/load
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else {
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else {
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cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
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cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3));
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}
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}
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// Connect control ports
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// Connect control ports
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cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
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cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
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cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
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cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1));
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// Connect config bits
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// Connect config bits
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cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6));
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cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6));
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cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0));
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cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0));
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// 3 - output post acc; 1 - output pre acc
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// 3 - output post acc; 1 - output pre acc
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cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
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cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3));
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bool subtract = (st.add->type == ID($sub));
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bool subtract = (st.add->type == ID($sub));
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cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
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cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0));
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// Mark the cells for removal
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// Mark the cells for removal
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pm.autoremove(st.mul);
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pm.autoremove(st.mul);
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pm.autoremove(st.add);
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pm.autoremove(st.add);
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if (st.mux != nullptr) {
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if (st.mux != nullptr) {
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pm.autoremove(st.mux);
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pm.autoremove(st.mux);
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}
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}
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pm.autoremove(st.ff);
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pm.autoremove(st.ff);
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}
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}
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struct QlDspMacc : public Pass {
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struct QlDspMacc : public Pass {
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@ -217,18 +216,18 @@ struct QlDspMacc : public Pass {
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void help() override
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void help() override
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{
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log("\n");
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log(" ql_dsp_macc [selection]\n");
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log(" ql_dsp_macc [selection]\n");
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log("\n");
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log("\n");
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log("This pass looks for a multiply-accumulate pattern based on which it infers a\n");
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log("This pass looks for a multiply-accumulate pattern based on which it infers a\n");
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log("QuickLogic DSP cell.\n");
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log("QuickLogic DSP cell.\n");
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log("\n");
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log("\n");
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}
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}
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
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{
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{
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int dsp_version = 1;
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int dsp_version = 1;
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log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
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log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
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size_t argidx;
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size_t argidx;
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@ -241,7 +240,7 @@ struct QlDspMacc : public Pass {
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}
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}
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extra_args(a_Args, argidx, a_Design);
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extra_args(a_Args, argidx, a_Design);
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auto l = [dsp_version](ql_dsp_macc_pm& pm) { create_ql_macc_dsp(pm, dsp_version); };
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auto l = [dsp_version](ql_dsp_macc_pm &pm) { create_ql_macc_dsp(pm, dsp_version); };
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for (auto module : a_Design->selected_modules())
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for (auto module : a_Design->selected_modules())
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(l);
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ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(l);
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}
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}
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