riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1871 from boqwxp/cleanup_splice 

Clean up `passes/cmds/splice.cc`.
This commit is contained in:
whitequark 2020-04-06 11:03:34 +00:00 committed by GitHub
parent db66371915 5e9c88501e
commit 41f0c38478
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 14 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
passes/cmds/splice.cc
View File

@ -102,7 +102,7 @@ struct SpliceWorker
for (auto &bit : sig.to_sigbit_vector()) for (auto &bit : sig.to_sigbit_vector())
{ {
if (bit.wire == NULL) if (bit.wire == nullptr)
{ {
if (last_bit == 0) if (last_bit == 0)
chunks.back().append(bit); chunks.back().append(bit);
@ -149,23 +149,23 @@ struct SpliceWorker
void run() void run()
{ {
log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name)); log("Splicing signals in module %s:\n", log_id(module->name));
driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm);
for (auto &it : module->wires_) for (auto wire : module->wires())
if (it.second->port_input) { if (wire->port_input) {
RTLIL::SigSpec sig = sigmap(it.second); RTLIL::SigSpec sig = sigmap(wire);
driven_chunks.insert(sig); driven_chunks.insert(sig);
for (auto &bit : sig.to_sigbit_vector()) for (auto &bit : sig.to_sigbit_vector())
driven_bits.push_back(bit); driven_bits.push_back(bit);
driven_bits.push_back(RTLIL::State::Sm); driven_bits.push_back(RTLIL::State::Sm);
} }
for (auto &it : module->cells_) for (auto cell : module->cells())
for (auto &conn : it.second->connections()) for (auto &conn : cell->connections())
if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first)) {
RTLIL::SigSpec sig = sigmap(conn.second); RTLIL::SigSpec sig = sigmap(conn.second);
driven_chunks.insert(sig); driven_chunks.insert(sig);
for (auto &bit : sig.to_sigbit_vector()) for (auto &bit : sig.to_sigbit_vector())
@ -180,9 +180,8 @@ struct SpliceWorker
SigPool selected_bits; SigPool selected_bits;
if (!sel_by_cell) if (!sel_by_cell)
for (auto &it : module->wires_) for (auto wire : module->selected_wires())
if (design->selected(module, it.second)) selected_bits.add(sigmap(wire));
selected_bits.add(sigmap(it.second));
std::vector<Cell*> mod_cells = module->cells(); std::vector<Cell*> mod_cells = module->cells();
@ -343,17 +342,14 @@ struct SplicePass : public Pass {
log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n"); log_header(design, "Executing SPLICE pass (creating cells for signal splicing).\n");
for (auto &mod_it : design->modules_) for (auto module : design->selected_modules())
{ {
if (!design->selected(mod_it.second)) if (module->processes.size()) {
continue; log("Skipping module %s as it contains processes.\n", module->name.c_str());
if (mod_it.second->processes.size()) {
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
continue; continue;
} }
SpliceWorker worker(design, mod_it.second); SpliceWorker worker(design, module);
worker.sel_by_cell = sel_by_cell; worker.sel_by_cell = sel_by_cell;
worker.sel_by_wire = sel_by_wire; worker.sel_by_wire = sel_by_wire;
worker.sel_any_bit = sel_any_bit; worker.sel_any_bit = sel_any_bit;