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add option to fsm_detect to ignore self-resetting

This commit is contained in:
N. Engelhardt 2023-01-20 15:10:59 +01:00 committed by N. Engelhardt
parent ecfa7e9fbc
commit 419f91a2b9
1 changed files with 22 additions and 7 deletions
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29
passes/fsm/fsm_detect.cc
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@ -118,7 +118,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
return true; return true;
} }
static void detect_fsm(RTLIL::Wire *wire) static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
{ {
bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none"; bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none"; bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
@ -199,7 +199,7 @@ static void detect_fsm(RTLIL::Wire *wire)
} }
SigSpec sig_y = sig_d, sig_undef; SigSpec sig_y = sig_d, sig_undef;
if (ce.eval(sig_y, sig_undef)) if (!ignore_self_reset && ce.eval(sig_y, sig_undef))
is_self_resetting = true; is_self_resetting = true;
} }
@ -261,12 +261,15 @@ struct FsmDetectPass : public Pass {
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" fsm_detect [selection]\n"); log(" fsm_detect [options] [selection]\n");
log("\n"); log("\n");
log("This pass detects finite state machines by identifying the state signal.\n"); log("This pass detects finite state machines by identifying the state signal.\n");
log("The state signal is then marked by setting the attribute 'fsm_encoding'\n"); log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
log("on the state signal to \"auto\".\n"); log("on the state signal to \"auto\".\n");
log("\n"); log("\n");
log(" -ignore-self-reset\n");
log(" Mark FSMs even if they are self-resetting\n");
log("\n");
log("Existing 'fsm_encoding' attributes are not changed by this pass.\n"); log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
log("\n"); log("\n");
log("Signals can be protected from being detected by this pass by setting the\n"); log("Signals can be protected from being detected by this pass by setting the\n");
@ -276,16 +279,28 @@ struct FsmDetectPass : public Pass {
log("before this pass to prepare the design for fsm_detect.\n"); log("before this pass to prepare the design for fsm_detect.\n");
log("\n"); log("\n");
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
log("The Verific frontend may merge multiplexers in a way that interferes with FSM\n"); log("The Verific frontend may optimize the design in a way that interferes with FSM\n");
log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n"); log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n");
log("reading the source, and 'bmuxmap' after 'proc' for best results.\n"); log("reading the source, and 'bmuxmap -pmux' after 'proc' for best results.\n");
log("\n"); log("\n");
#endif #endif
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n"); log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
extra_args(args, 1, design);
bool ignore_self_reset = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-ignore-self-reset") {
ignore_self_reset = true;
continue;
}
break;
}
extra_args(args, argidx, design);
CellTypes ct; CellTypes ct;
ct.setup_internals(); ct.setup_internals();
@ -321,7 +336,7 @@ struct FsmDetectPass : public Pass {
sig_at_port.add(assign_map(wire)); sig_at_port.add(assign_map(wire));
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
detect_fsm(wire); detect_fsm(wire, ignore_self_reset);
} }
assign_map.clear(); assign_map.clear();