riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Revert "Fold loop" 

This reverts commit a30d5e1cc3.
This commit is contained in:
Eddie Hung 2019-11-27 21:55:56 -08:00
parent 6464dc35ec
commit 419ca5c207
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
backends/aiger/xaiger.cc
View File

@ -174,7 +174,6 @@ struct XAigerWriter
if (bit != wirebit) if (bit != wirebit)
alias_map[bit] = wirebit; alias_map[bit] = wirebit;
input_bits.insert(wirebit); input_bits.insert(wirebit);
undriven_bits.erase(bit);
} }
if (wire->port_output || keep) { if (wire->port_output || keep) {
@ -182,8 +181,6 @@ struct XAigerWriter
if (bit != wirebit) if (bit != wirebit)
alias_map[wirebit] = bit; alias_map[wirebit] = bit;
output_bits.insert(wirebit); output_bits.insert(wirebit);
if (!wire->port_input)
unused_bits.erase(bit);
} }
else else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@ -191,6 +188,12 @@ struct XAigerWriter
} }
} }
for (auto bit : input_bits)
undriven_bits.erase(sigmap(bit));
for (auto bit : output_bits)
if (!bit.wire->port_input)
unused_bits.erase(bit);
// TODO: Speed up toposort -- ultimately we care about // TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells // box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users; dict<SigBit, pool<IdString>> bit_drivers, bit_users;