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Fixed performance bug in Verific importer

This commit is contained in:
Clifford Wolf 2015-11-16 12:38:56 +01:00
parent b18f3a2974
commit 415e0a1b90
1 changed files with 12 additions and 10 deletions
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22
frontends/verific/verific.cc
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@ -745,6 +745,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), inst->IsOperator() ? RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), inst->IsOperator() ?
std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name())); std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name()));
dict<IdString, vector<SigBit>> cell_port_conns;
FOREACH_PORTREF_OF_INST(inst, mi2, pr) { FOREACH_PORTREF_OF_INST(inst, mi2, pr) {
// log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name()); // log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name());
const char *port_name = pr->GetPort()->Name(); const char *port_name = pr->GetPort()->Name();
@ -754,16 +756,16 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) - port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex()); min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
} }
RTLIL::SigSpec conn; IdString port_name_id = RTLIL::escape_id(port_name);
if (cell->hasPort(RTLIL::escape_id(port_name))) auto &sigvec = cell_port_conns[port_name_id];
conn = cell->getPort(RTLIL::escape_id(port_name)); if (GetSize(sigvec) <= port_offset)
while (GetSize(conn) <= port_offset) { sigvec.resize(port_offset+1, State::Sz);
if (pr->GetPort()->GetDir() != DIR_IN) sigvec[port_offset] = net_map.at(pr->GetNet());
conn.append(module->addWire(NEW_ID, port_offset - GetSize(conn))); }
conn.append(RTLIL::State::Sz);
} for (auto &it : cell_port_conns) {
conn.replace(port_offset, net_map.at(pr->GetNet())); // log(" .%s(%s)\n", log_id(it.first), log_signal(it.second));
cell->setPort(RTLIL::escape_id(port_name), conn); cell->setPort(it.first, it.second);
} }
} }
} }