diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index 544095081..6e6a96035 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -82,7 +82,8 @@ static void nx_carry_chain(Module *module)
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
 		if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
-			cell->setPort(ID(CI), State::S0);
+			cell->setParam(ID(add_carry), Const(1,2));
+			cell->setPort(ID(CI), State::S1);
 
 			cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
 			cell->setPort(names_B[0], State::S0);
@@ -104,13 +105,14 @@ static void nx_carry_chain(Module *module)
 				}
 			}
 			if (j==3) {
-				if (cnt % 24 == 23) {
+				if (cnt !=0 && (cnt % 24 == 0)) {
 					SigBit new_co = module->addWire(NEW_ID);
 					cell->setPort(ID(A4), State::S0);
 					cell->setPort(ID(B4), State::S0);
 					cell->setPort(ID(S4), new_co);
 					cell = module->addCell(NEW_ID, ID(NX_CY));
-					cell->setPort(ID(CI), State::S0);
+					cell->setParam(ID(add_carry), Const(1,2));
+					cell->setPort(ID(CI), State::S1);
 					cell->setPort(ID(A1), new_co);
 					cell->setPort(ID(B1), State::S0);
 					j = 1;
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
index 0cfc201f5..9b23cef15 100644
--- a/tests/arch/nanoxplore/add_sub.ys
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -1,10 +1,71 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
-equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 2 t:NX_CY
 select -assert-count 4 t:NX_LUT
 select -assert-none t:NX_CY t:NX_LUT %% t:* %D
 
+design -reset
+read_verilog <<EOT
+module top
+(
+    input [5:0] x,
+    input [5:0] y,
+
+    output [5:0] A,
+    input CI,
+    output CO
+);
+
+    assign {CO, A} =  x + y + CI;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+stat
+select -assert-count 2 t:NX_CY
+select -assert-none t:NX_CY %% t:* %D
+
+design -reset
+read_verilog <<EOT
+module top
+(
+    input [189:0] x,
+    input [189:0] y,
+
+    output [189:0] A
+);
+
+    assign A =  x + y;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+stat
+select -assert-count 48 t:NX_CY
+select -assert-none t:NX_CY %% t:* %D
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