riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added "check -noinit"

This commit is contained in:
Clifford Wolf 2015-02-15 12:58:12 +01:00
parent a54c994e2b
commit 40f021e136
1 changed files with 19 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
passes/cmds/check.cc
View File

@ -31,7 +31,7 @@ struct CheckPass : public Pass {
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" check [selection]\n"); log(" check [options] [selection]\n");
log("\n"); log("\n");
log("This pass identifies the following problems in the current design:\n"); log("This pass identifies the following problems in the current design:\n");
log("\n"); log("\n");
@ -41,15 +41,27 @@ struct CheckPass : public Pass {
log("\n"); log("\n");
log(" - used wires that do not have a driver\n"); log(" - used wires that do not have a driver\n");
log("\n"); log("\n");
log("When called with -noinit then this command also checks for wires which have\n");
log("the 'init' attribute set.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
int counter = 0; int counter = 0;
bool noinit = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-noinit") {
noinit = true;
continue;
}
break;
}
extra_args(args, argidx, design);
log_header("Executing CHECK pass (checking for obvious problems).\n"); log_header("Executing CHECK pass (checking for obvious problems).\n");
extra_args(args, 1, design);
for (auto module : design->selected_whole_modules_warn()) for (auto module : design->selected_whole_modules_warn())
{ {
if (module->has_processes_warn()) if (module->has_processes_warn())
@ -93,6 +105,10 @@ struct CheckPass : public Pass {
if (wire->port_output) if (wire->port_output)
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
if (bit.wire) used_wires.insert(bit); if (bit.wire) used_wires.insert(bit);
if (noinit && wire->attributes.count("\\init")) {
log_warning("Wire %s.%s has an unprocessed 'init' attribute.\n", log_id(module), log_id(wire));
counter++;
}
} }
for (auto it : wire_drivers) for (auto it : wire_drivers)