From 40c690b0305b15e51d7dec2e2b5ca1051c37be95 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Wed, 30 Oct 2024 17:30:44 +0100
Subject: [PATCH] extract_fa: Add test case

---
 tests/various/bug3879.ys | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 tests/various/bug3879.ys

diff --git a/tests/various/bug3879.ys b/tests/various/bug3879.ys
new file mode 100644
index 000000000..7163a1f56
--- /dev/null
+++ b/tests/various/bug3879.ys
@@ -0,0 +1,29 @@
+read_verilog <<EOF
+module gcd(I, D);
+
+  output [2:0] I;
+  input [3:0] D;
+
+  assign I = D[0]+D[1]+D[2]+D[3];
+endmodule
+EOF
+design -save input
+
+prep
+
+design -stash gold
+
+design -load input
+
+synth  -top gcd -flatten
+
+extract_fa -v
+
+design -stash gate
+
+design -copy-from gold -as gold gcd
+design -copy-from gate -as gate gcd
+
+miter -equiv -make_assert -flatten gold gate miter
+
+sat -verify -prove-asserts -show-all miter