riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Improved xilinx mojo_counter example

This commit is contained in:
Clifford Wolf 2013-10-26 22:28:42 +02:00
parent ceb971eab9
commit 4007b41d40
2 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
techlibs/xilinx7/example_mojo_counter/example.sh
View File

@ -19,11 +19,14 @@ abc -lut 6; opt
# map internal cells to FPGA cells # map internal cells to FPGA cells
techmap -map ../cells.v; opt techmap -map ../cells.v; opt
# insert i/o buffers
iopadmap -outpad OBUF I:O -inpad BUFGP O:I
# write netlist # write netlist
write_edif synth.edif write_edif synth.edif
EOT EOT
cat > synth.ut <<- EOT cat > bitgen.ut <<- EOT
-w -w
-g DebugBitstream:No -g DebugBitstream:No
-g Binary:no -g Binary:no

2
techlibs/xilinx7/example_mojo_counter/example.v
View File

@ -7,7 +7,7 @@ output led_3, led_2, led_1, led_0;
reg [31:0] counter; reg [31:0] counter;
always @(posedge clk) always @(posedge clk)
counter <= counter + 1; counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24; assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;