Merge remote-tracking branch 'origin/master' into xc7dsp

CHANGELOG

@@ -41,6 +41,8 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
     - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
     - Added "-match-init" option to "dff2dffs" pass
+    - Added "techmap_autopurge" support to techmap
+    - Added "add -mod <modname[s]>"
     - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
     - Added "ice40_dsp" for Lattice iCE40 DSP packing
     - Added "xilinx_dsp" for Xilinx DSP packing

frontends/ast/ast.cc

@@ -158,6 +158,11 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_POSEDGE)
 	X(AST_NEGEDGE)
 	X(AST_EDGE)
+	X(AST_INTERFACE)
+	X(AST_INTERFACEPORT)
+	X(AST_INTERFACEPORTTYPE)
+	X(AST_MODPORT)
+	X(AST_MODPORTMEMBER)
 	X(AST_PACKAGE)
 #undef X
 	default:
@@ -1291,6 +1296,8 @@ void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule
 // from AST. The interface members are copied into the AST module with the prefix of the interface.
 void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
 {
+	loadconfig();
+
 	bool is_top = false;
 	AstNode *new_ast = ast->clone();
 	for (auto &intf : local_interfaces) {
@@ -1474,24 +1481,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 		stripped_name = stripped_name.substr(9);
 
 	log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
-
-	current_ast = NULL;
-	flag_dump_ast1 = false;
-	flag_dump_ast2 = false;
-	flag_dump_vlog1 = false;
-	flag_dump_vlog2 = false;
-	flag_nolatches = nolatches;
-	flag_nomeminit = nomeminit;
-	flag_nomem2reg = nomem2reg;
-	flag_mem2reg = mem2reg;
-	flag_noblackbox = noblackbox;
-	flag_lib = lib;
-	flag_nowb = nowb;
-	flag_noopt = noopt;
-	flag_icells = icells;
-	flag_pwires = pwires;
-	flag_autowire = autowire;
-	use_internal_line_num();
+	loadconfig();
 
 	std::string para_info;
 	AstNode *new_ast = ast->clone();
@@ -1572,6 +1562,27 @@ RTLIL::Module *AstModule::clone() const
 	return new_mod;
 }
 
+void AstModule::loadconfig() const
+{
+	current_ast = NULL;
+	flag_dump_ast1 = false;
+	flag_dump_ast2 = false;
+	flag_dump_vlog1 = false;
+	flag_dump_vlog2 = false;
+	flag_nolatches = nolatches;
+	flag_nomeminit = nomeminit;
+	flag_nomem2reg = nomem2reg;
+	flag_mem2reg = mem2reg;
+	flag_noblackbox = noblackbox;
+	flag_lib = lib;
+	flag_nowb = nowb;
+	flag_noopt = noopt;
+	flag_icells = icells;
+	flag_pwires = pwires;
+	flag_autowire = autowire;
+	use_internal_line_num();
+}
+
 // internal dummy line number callbacks
 namespace {
 	int internal_line_num;

frontends/ast/ast.h

@@ -299,6 +299,7 @@ namespace AST
 		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
 		void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
 		RTLIL::Module *clone() const YS_OVERRIDE;
+		void loadconfig() const;
 	};
 
 	// this must be set by the language frontend before parsing the sources

passes/cmds/add.cc

@@ -105,6 +105,11 @@ struct AddPass : public Pass {
 		log("Like 'add -input', but also connect the signal between instances of the\n");
 		log("selected modules.\n");
 		log("\n");
+		log("\n");
+		log("    add -mod <name[s]>\n");
+		log("\n");
+		log("Add module[s] with the specified name[s].\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -113,6 +118,7 @@ struct AddPass : public Pass {
 		bool arg_flag_input = false;
 		bool arg_flag_output = false;
 		bool arg_flag_global = false;
+		bool mod_mode = false;
 		int arg_width = 0;
 
 		size_t argidx;
@@ -133,8 +139,20 @@ struct AddPass : public Pass {
 				arg_width = atoi(args[++argidx].c_str());
 				continue;
 			}
+			if (arg == "-mod") {
+				mod_mode = true;
+				argidx++;
 				break;
 			}
+			break;
+		}
+
+		if (mod_mode) {
+			for (; argidx < args.size(); argidx++)
+				design->addModule(RTLIL::escape_id(args[argidx]));
+			return;
+		}
+
 		extra_args(args, argidx, design);
 
 		for (auto &mod : design->modules_)