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Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys into xaig_arrival

This commit is contained in:
Eddie Hung 2019-08-23 13:46:17 -07:00
parent 48c424e45b 3c1c376fb1
commit 3fa826254f
2 changed files with 1 additions and 14 deletions
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13
techlibs/ecp5/abc_model.v
View File

@ -3,16 +3,3 @@
(* abc_box_id=2 *)
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
endmodule
module \$__ABC_DPR16X4_SEQ (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
endmodule

2
techlibs/ecp5/cells_sim.v
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@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
input WCK,
input [3:0] RAD,
/* (* abc_arrival=<TODO> *) */
output [3:0] DO
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";