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abstract: test -slice from:to for -init
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@ -52,10 +52,16 @@ EOT
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proc
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opt_expr
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opt_dff
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design -save basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -load basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0:1 w:Q
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check -assert
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select -assert-count 0 w:Q a:init %i
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design -reset
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read_verilog <<EOT
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