mirror of https://github.com/YosysHQ/yosys.git
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
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@ -603,63 +603,66 @@ struct SatGen
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std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
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std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
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char shift_left = cell->type == "$shl" || cell->type == "$sshl";
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bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool();
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bool shift_shiftx = cell->type == "$shift" || cell->type == "$shiftx";
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int extend_bit = ez->FALSE;
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if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
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extend_bit = a.back();
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while (y.size() < a.size())
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y.push_back(ez->literal());
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while (y.size() > a.size())
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a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE);
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a.push_back(extend_bit);
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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std::vector<int> shifted_a;
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std::vector<int> tmp = a;
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for (size_t i = 0; i < b.size(); i++)
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{
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bool shift_left_this = shift_left;
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if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool())
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shift_left_this = true;
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if (cell->type == "$shl" || cell->type == "$sshl")
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shifted_a = ez->vec_shift_left(a, b, false, ez->FALSE, ez->FALSE);
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std::vector<int> tmp_shifted(tmp.size());
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for (size_t j = 0; j < tmp.size(); j++) {
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int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1);
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tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE;
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}
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tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);
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}
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ez->assume(ez->vec_eq(tmp, yy));
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if (cell->type == "$shr")
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shifted_a = ez->vec_shift_right(a, b, false, ez->FALSE, ez->FALSE);
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if (cell->type == "$sshr")
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shifted_a = ez->vec_shift_right(a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? a.back() : ez->FALSE, ez->FALSE);
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if (cell->type == "$shift" || cell->type == "$shiftx")
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shifted_a = ez->vec_shift_right(a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
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ez->assume(ez->vec_eq(shifted_a, yy));
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if (model_undef)
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{
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std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
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std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
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std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
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std::vector<int> undef_a_shifted;
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if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
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extend_bit = undef_a.back();
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while (undef_y.size() < undef_a.size())
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undef_y.push_back(ez->literal());
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while (undef_y.size() > undef_a.size())
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undef_a.push_back(cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE);
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undef_a.push_back(extend_bit);
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tmp = undef_a;
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for (size_t i = 0; i < b.size(); i++)
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{
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bool shift_left_this = shift_left;
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if (shift_shiftx && i == b.size()-1 && cell->parameters["\\B_SIGNED"].as_bool())
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shift_left_this = true;
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if (cell->type == "$shl" || cell->type == "$sshl")
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undef_a_shifted = ez->vec_shift_left(undef_a, b, false, ez->FALSE, ez->FALSE);
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std::vector<int> tmp_shifted(tmp.size());
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for (size_t j = 0; j < tmp.size(); j++) {
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int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left_this ? -1 : +1);
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tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) :
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sign_extend ? tmp.back() : cell->type == "$shiftx" ? ez->TRUE : ez->FALSE;
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}
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tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);
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}
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if (cell->type == "$shr")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->FALSE, ez->FALSE);
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if (cell->type == "$sshr")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters["\\A_SIGNED"].as_bool() ? undef_a.back() : ez->FALSE, ez->FALSE);
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if (cell->type == "$shift")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->FALSE, ez->FALSE);
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if (cell->type == "$shiftx")
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters["\\B_SIGNED"].as_bool(), ez->TRUE, ez->TRUE);
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int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
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std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
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ez->assume(ez->vec_eq(ez->vec_or(tmp, undef_all_y_bits), undef_y));
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ez->assume(ez->vec_eq(ez->vec_or(undef_a_shifted, undef_all_y_bits), undef_y));
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undefGating(y, yy, undef_y);
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}
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return true;
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