mirror of https://github.com/YosysHQ/yosys.git
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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9e5ff30d05
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@ -1893,10 +1893,6 @@ DEF_METHOD(And, max(sig_a.size(), sig_b.size()), ID($and))
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DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
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DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
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DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
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DEF_METHOD(Shl, sig_a.size(), ID($shl))
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DEF_METHOD(Shr, sig_a.size(), ID($shr))
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DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
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DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
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DEF_METHOD(Shift, sig_a.size(), ID($shift))
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DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
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DEF_METHOD(Lt, 1, ID($lt))
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@ -1916,6 +1912,31 @@ DEF_METHOD(LogicAnd, 1, ID($logic_and))
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DEF_METHOD(LogicOr, 1, ID($logic_or))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _y_size, _type) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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cell->parameters[ID(A_SIGNED)] = is_signed; \
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cell->parameters[ID(B_SIGNED)] = false; \
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cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
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cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
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cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
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cell->setPort(ID::A, sig_a); \
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cell->setPort(ID::B, sig_b); \
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cell->setPort(ID::Y, sig_y); \
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cell->set_src_attribute(src); \
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return cell; \
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} \
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RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed, const std::string &src) { \
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RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
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add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
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return sig_y; \
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}
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DEF_METHOD(Shl, sig_a.size(), ID($shl))
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DEF_METHOD(Shr, sig_a.size(), ID($shr))
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DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
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DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _type, _pmux) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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